[PATCH] D72683: [PowerPC] set instruction number as 1st priority for lsr cost model

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
shchenz added reviewers: jsji, nemanjai, steven.zhang, hfinkel, PowerPC.
Herald added subscribers: llvm-commits, wuzish, asbirlea, hiraditya.
Herald added a project: LLVM.

This issue comes from case in file `test/CodeGen/PowerPC/lsr-insns-cost.ll`

Three iteration IVs are used while we expect one. This is because, on PowerPC, register number is 1st priority for lsr cost model now.

This patch changes instruction number as 1st priority.

Tested perf on Power9, cpu2017 benchmark x264 gets about 3% improvement, imagick gains about %2 for BASE 1-copy.
No obvious deg found on cpu2017 benchmarks on Power9.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D72683

Files:
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
  llvm/test/CodeGen/PowerPC/addi-licm.ll
  llvm/test/CodeGen/PowerPC/lsr-insns-cost.ll
  llvm/test/CodeGen/PowerPC/unal-altivec.ll


Index: llvm/test/CodeGen/PowerPC/unal-altivec.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/unal-altivec.ll
+++ llvm/test/CodeGen/PowerPC/unal-altivec.ll
@@ -29,14 +29,15 @@
   br i1 %10, label %for.end, label %vector.body
 
 ; CHECK: @foo
-; CHECK-DAG: li [[C16:[0-9]+]], 16
+; CHECK-DAG: li [[C0:[0-9]+]], 0
 ; CHECK-DAG: lvx [[CNST:[0-9]+]],
 ; CHECK: .LBB0_1:
-; CHECK-DAG: lvx [[LD1:[0-9]+]], 0, [[C0:[0-9]+]]
-; CHECK-DAG: lvx [[LD2:[0-9]+]], [[C0]], [[C16]]
-; CHECK-DAG: lvsl [[MASK1:[0-9]+]], 0, [[C0]]
-; CHECK-DAG: vperm [[VR1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
-; CHECK-DAG: vaddfp {{[0-9]+}}, [[VR1]], [[CNST]]
+; CHECK-DAG: lvsl [[MASK1:[0-9]+]], [[B1:[0-9]+]], [[C0]]
+; CHECK-DAG: add [[B3:[0-9]+]], [[B1]], [[C0]]
+; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
+; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]],
+; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
+; CHECK-DAG: vaddfp {{[0-9]+}}, [[R1]], [[CNST]]
 ; CHECK: blr
 
 for.end:                                          ; preds = %vector.body
Index: llvm/test/CodeGen/PowerPC/lsr-insns-cost.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/lsr-insns-cost.ll
+++ llvm/test/CodeGen/PowerPC/lsr-insns-cost.ll
@@ -12,13 +12,11 @@
 define void @lsr-insts-cost(i32* %0, i32* %1, i32* %2) {
 ; CHECK-LABEL: lsr-insts-cost
 ; CHECK:       .LBB0_4: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    lxvd2x vs34, 0, r3
-; CHECK-NEXT:    lxvd2x vs35, 0, r4
-; CHECK-NEXT:    addi r4, r4, 16
-; CHECK-NEXT:    addi r3, r3, 16
+; CHECK-NEXT:    lxvd2x vs34, r3, r6
+; CHECK-NEXT:    lxvd2x vs35, r4, r6
 ; CHECK-NEXT:    vadduwm v2, v3, v2
-; CHECK-NEXT:    stxvd2x vs34, 0, r5
-; CHECK-NEXT:    addi r5, r5, 16
+; CHECK-NEXT:    stxvd2x vs34, r5, r6
+; CHECK-NEXT:    addi r6, r6, 16
 ; CHECK-NEXT:    bdnz .LBB0_4
   %4 = getelementptr i32, i32* %2, i64 1024
   %5 = getelementptr i32, i32* %0, i64 1024
Index: llvm/test/CodeGen/PowerPC/addi-licm.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/addi-licm.ll
+++ llvm/test/CodeGen/PowerPC/addi-licm.ll
@@ -17,9 +17,10 @@
 ; CHECK-LABEL: @foo
 ; CHECK: addi [[REG1:[0-9]+]], 1,
 ; CHECK: addi [[REG2:[0-9]+]], 1,
+; CHECK: li [[REG3:[0-9]+]], 0
 ; CHECK: %for.body.i
-; CHECK-DAG: lfs {{[0-9]+}}, 0([[REG1]])
-; CHECK-DAG: lfs {{[0-9]+}}, 0([[REG2]])
+; CHECK-DAG: lfsx {{[0-9]+}}, [[REG1]], [[REG3]]
+; CHECK-DAG: lfsx {{[0-9]+}}, [[REG2]], [[REG3]]
 ; CHECK: blr
 
 ; PIP-LABEL: @foo
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
===================================================================
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
@@ -63,6 +63,8 @@
                   TargetLibraryInfo *LibInfo);
   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
                                TTI::UnrollingPreferences &UP);
+  bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
+                     TargetTransformInfo::LSRCost &C2);
 
   /// @}
 
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -967,3 +967,12 @@
   *BI = HWLoopInfo.ExitBranch;
   return true;
 }
+
+bool PPCTTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1,
+                               TargetTransformInfo::LSRCost &C2) {
+  // PowerPC specific here are "instruction number 1st priority".
+  return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, C1.NumIVMuls,
+                  C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
+         std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, C2.NumIVMuls,
+                  C2.NumBaseAdds, C2.ScaleCost, C2.ImmCost, C2.SetupCost);
+}


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