[PATCH] D72673: [PowerPC] Fix powerpcspe subtarget enablement in llvm backend
Justin Hibbits via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 13 18:14:10 PST 2020
jhibbits created this revision.
jhibbits added reviewers: PowerPC, MaskRay.
Herald added subscribers: llvm-commits, steven.zhang, shchenz, jsji, kbarton, hiraditya, nemanjai.
Herald added a project: LLVM.
As currently written, -target powerpcspe will enable SPE regardless of
disabling the feature later on in the command line. Instead, change
this to just set a default CPU to 'e500' instead of a generic CPU.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D72673
Files:
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -127,6 +127,8 @@
// If cross-compiling with -march=ppc64le without -mcpu
if (TargetTriple.getArch() == Triple::ppc64le)
CPUName = "ppc64le";
+ else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
+ CPUName = "e500";
else
CPUName = "generic";
}
@@ -151,9 +153,6 @@
TargetTriple.isMusl())
SecurePlt = true;
- if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
- HasSPE = true;
-
if (HasSPE && IsPPC64)
report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU))
Index: llvm/lib/Target/PowerPC/PPC.td
===================================================================
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -442,7 +442,7 @@
def : ProcessorModel<"e500", PPCE500Model,
[DirectiveE500,
FeatureICBT, FeatureBookE,
- FeatureISEL, FeatureMFTB]>;
+ FeatureISEL, FeatureMFTB, FeatureSPE]>;
def : ProcessorModel<"e500mc", PPCE500mcModel,
[DirectiveE500mc,
FeatureSTFIWX, FeatureICBT, FeatureBookE,
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