[PATCH] D70790: [ARM] Favour post inc for MVE loops

[Dave Green via Phabricator via llvm-commits]

dmgreen updated this revision to Diff 237627.
dmgreen marked an inline comment as done.
dmgreen added a comment.

Sorry for the long delay here. This wasn't making things much better in the tests I was trying (it was a bit up-and-down). I've adjusted it now to include shouldFavorPostInc for MVE subtargets, not just disable shouldFavorBackedgeIndex. That should get the costmodel more correct in LSR, where the AddRec is now free because it can just be the postinc. I also removed the old "containsVectors(L)" check as adding something that is O(n) to the inner parts of LSR, something that is already O(something large), was probably a bad idea.

This means that it's just based on subtarget. I was hoping I could add Type here and use that, but the only type we have in LSR is the type of the SCEV, not the type of the memory being loaded (i.e just a pointer, not a vector). My benchmarking shows this to be an improvement (even if a bit of an unreliable one). More so with D71194 <https://reviews.llvm.org/D71194>. The argument is that most simple loops are vectorized, not unrolled, so favouring post-inc is a slightly better alternative in general when we have MVE.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70790/new/

https://reviews.llvm.org/D70790

Files:
  llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
  llvm/lib/Target/ARM/ARMTargetTransformInfo.h
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
  llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
  llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll
  llvm/test/CodeGen/Thumb2/mve-vldst4.ll
  llvm/test/CodeGen/Thumb2/mve-vmla.ll

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