[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Evandro Menezes via Phabricator via llvm-commits]

evandro added a comment.

It seems to me that all remarks have already been addressed.  Is there anything holding this patch?  For it pretty much LGTM.



================
Comment at: llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h:50
+
+  InstVectorWithMask = (0x1 << 5),
 };
----------------
Why not just `32`?


Repository:
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  https://reviews.llvm.org/D69987/new/

https://reviews.llvm.org/D69987