[llvm] ddfcd82 - [LegalizeVectorOps] Expand vector MERGE_VALUES immediately.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-01-11T17:50:20-08:00
New Revision: ddfcd82bdc219dd2dc04d6826c417cea3da65d12

URL: https://github.com/llvm/llvm-project/commit/ddfcd82bdc219dd2dc04d6826c417cea3da65d12
DIFF: https://github.com/llvm/llvm-project/commit/ddfcd82bdc219dd2dc04d6826c417cea3da65d12.diff

LOG: [LegalizeVectorOps] Expand vector MERGE_VALUES immediately.

Custom legalization can produce MERGE_VALUES to return multiple
results. We can expand them immediately instead of leaving them
around for DAG combine to clean up.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index d6de85b3c83c..9316823d20e6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -332,6 +332,13 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
   switch (Op.getOpcode()) {
   default:
     return TranslateLegalizeResults(Op, Node);
+  case ISD::MERGE_VALUES:
+    Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
+    // This operation lies about being legal: when it claims to be legal,
+    // it should actually be expanded.
+    if (Action == TargetLowering::Legal)
+      Action = TargetLowering::Expand;
+    break;
 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN)                   \
   case ISD::STRICT_##DAGN:
 #include "llvm/IR/ConstrainedOps.def"
@@ -834,6 +841,10 @@ SDValue VectorLegalizer::ExpandStore(SDNode *N) {
 void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
   SDValue Tmp;
   switch (Node->getOpcode()) {
+  case ISD::MERGE_VALUES:
+    for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
+      Results.push_back(Node->getOperand(i));
+    return;
   case ISD::SIGN_EXTEND_INREG:
     Results.push_back(ExpandSEXTINREG(Node));
     return;