[PATCH] D72467: [WIP] Remove "mask" operand from shufflevector.
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 9 10:33:55 PST 2020
efriedma created this revision.
Herald added subscribers: dmgreen, hiraditya.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.
Instead, represent the mask as out-of-line data in the instruction. This
should be more efficient in the places that currently use
getShuffleVector(), and paves the way for further changes to add new
shuffles for scalable vectors.
This doesn't change the syntax in textual IR. And I don't currently plan
to change the bitcode encoding in this patch, although we'll probably
need to do something once we extend shufflevector for scalable types.
The biggest part of the patch that still doesn't work is the bitcode
writer/reader bits. It turns out to be a bit more complicated than I
anticipated. For writing, my attempt at conjuring the constant out of
thin air doesn't really work out because it needs to be found earlier;
not sure how I'll fix this. For reading, we need to change the way we
construct constant expressions, I think; currently, we can sometimes
construct an expression before its operands, which doesn't really work
out here.
There are a few other smaller cleanups I'd want to do here, but the new
APIs are in essentially the form I expect them to take in the final
patch.
I expect that once this is finished, we can then replace the raw "mask"
with something more appropriate for scalable vectors. Not sure exactly
what this looks like at the moment, but there are a few different ways
we could handle it. Maybe we could try to describe specific shuffles.
Or maybe we could define it in terms of a function to convert a fixed-length
array into an appropriate scalable vector, using a "step", or something
like that.
The big question here, of course, is "do we want to do this?", and if we
do, "do we want to do this now?". For the immediate needs of SVE, we
don't need fully general shuffles; we have intriniscs for the native
instructions, and we can add additional intrinsics or intrinsic
overloads for the various "extended" patterns we expect to need in the
immediate future that don't involve native SVE vectors, like
concatenating two "<vscale x 2 x i1>" vectors. The biggest risk if we
don't prioritize fixing shufflevector is that we end up duplicating work
when we add another target supporting vscale.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D72467
Files:
llvm/include/llvm/Analysis/ConstantFolding.h
llvm/include/llvm/Analysis/InstructionSimplify.h
llvm/include/llvm/IR/Constants.h
llvm/include/llvm/IR/Instructions.h
llvm/include/llvm/IR/PatternMatch.h
llvm/lib/Analysis/ConstantFolding.cpp
llvm/lib/Analysis/InstructionSimplify.cpp
llvm/lib/Analysis/TargetTransformInfo.cpp
llvm/lib/Analysis/ValueTracking.cpp
llvm/lib/Analysis/VectorUtils.cpp
llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
llvm/lib/CodeGen/CodeGenPrepare.cpp
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/IR/AsmWriter.cpp
llvm/lib/IR/ConstantFold.cpp
llvm/lib/IR/ConstantFold.h
llvm/lib/IR/Constants.cpp
llvm/lib/IR/ConstantsContext.h
llvm/lib/IR/Instruction.cpp
llvm/lib/IR/Instructions.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/MVETailPredication.cpp
llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
llvm/lib/Transforms/Scalar/ConstantProp.cpp
llvm/lib/Transforms/Scalar/GVN.cpp
llvm/lib/Transforms/Scalar/GVNSink.cpp
llvm/lib/Transforms/Scalar/NewGVN.cpp
llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/unittests/IR/PatternMatch.cpp
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