[llvm] db7c920 - AMDGPU: Add register class to DS_SWIZZLE_B32 pattern

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-01-09T10:29:31-05:00
New Revision: db7c92077963195df0807e976cc916b5c6e29a05

URL: https://github.com/llvm/llvm-project/commit/db7c92077963195df0807e976cc916b5c6e29a05
DIFF: https://github.com/llvm/llvm-project/commit/db7c92077963195df0807e976cc916b5c6e29a05.diff

LOG: AMDGPU: Add register class to DS_SWIZZLE_B32 pattern

Reduces diff for a future patch.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/DSInstructions.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index f008b800bd32..f0987cffd106 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -619,7 +619,7 @@ def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
 
 def : GCNPat <
   (int_amdgcn_ds_swizzle i32:$src, timm:$offset16),
-  (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
+  (DS_SWIZZLE_B32 VGPR_32:$src, (as_i16imm $offset16), (i1 0))
 >;
 
 class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <