[PATCH] D71568: [InstCombine] `select + mul` -> `select + shl` with power of twos.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

Sorry, i lost track of this patch.
I was hoping someone more familiar with that code would comment, too.



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Comment at: llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp:333-338
+  if (match(Op1, m_Shl(m_One(), m_Value())) ||
+      match(Op1, m_NSWShl(m_Power2(), m_Value())) ||
+      match(Op1, m_NUWShl(m_Power2(), m_Value())) ||
+      match(Op1, m_ZExt(m_Shl(m_One(), m_Value()))) ||
+      match(Op1, m_ZExt(m_NSWShl(m_Power2(), m_Value()))) ||
+      match(Op1, m_ZExt(m_NUWShl(m_Power2(), m_Value())))) {
----------------
You can at least cut this in half by using `m_ZExtOrSelf()`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71568/new/

https://reviews.llvm.org/D71568