[PATCH] D72361: [DAGCombiner] reduce extract subvector of concat

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D72361#1810410 <https://reviews.llvm.org/D72361#1810410>, @lebedev.ri wrote:

> In D72361#1810243 <https://reviews.llvm.org/D72361#1810243>, @spatel wrote:
>
> > Patch updated:
> >  Made predicate more restrictive and added asserts.
>
>
> Can a test case be constructed for that?
>
> > (That case could be implemented as a shuffle, if we don't do that already)


This takes some creativity because we won't generate the needed DAG nodes if the types are too weird and/or mapped to registers in a strange way, but I've found a case that is legal enough to show what would have been a miscompile:
define <4 x i32> @cat_ext_straddle(<6 x i32>* %px, <6 x i32>* %py) {

  %x = load <6 x i32>, <6 x i32>* %px
  %y = load <6 x i32>, <6 x i32>* %py
  %cat = shufflevector <6 x i32> %x, <6 x i32> %y, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
  %ext = shufflevector <12 x i32> %cat, <12 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  ret <4 x i32> %ext

}

Should be:

  movaps	16(%rdi), %xmm0
  unpcklpd	(%rsi), %xmm0   ## xmm0 = xmm0[0],mem[0]

But would be miscompiled by the earlier rev of this patch:

  movaps	16(%rdi), %xmm0

rG31992a69b808 <https://reviews.llvm.org/rG31992a69b808f30a46a4ddb6da0d073d528bc72e>


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72361/new/

https://reviews.llvm.org/D72361