[llvm] d60b3b4 - [X86] Add isel patterns for bitcasting between v32i1/v64i1 and float/double.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-01-08T10:06:01-08:00
New Revision: d60b3b4817cb9346b682bb75371c41642c273b13

URL: https://github.com/llvm/llvm-project/commit/d60b3b4817cb9346b682bb75371c41642c273b13
DIFF: https://github.com/llvm/llvm-project/commit/d60b3b4817cb9346b682bb75371c41642c273b13.diff

LOG: [X86] Add isel patterns for bitcasting between v32i1/v64i1 and float/double.

We have to do an intermediate jump to a GPR to make the cast.

Fixes PR43750.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86InstrAVX512.td
    llvm/test/CodeGen/X86/avx512bw-mask-op.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 0b263acbc95e..ebb22ec270ea 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -3932,6 +3932,17 @@ def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
                 (VMOVPQIto64Zrr GR64:$dst, VR128X:$src), 0>;
 
+// Conversions between masks and scalar fp.
+def : Pat<(v32i1 (bitconvert FR32X:$src)),
+          (KMOVDkr (VMOVSS2DIZrr FR32X:$src))>;
+def : Pat<(f32 (bitconvert VK32:$src)),
+          (VMOVDI2SSZrr (KMOVDrk VK32:$src))>;
+
+def : Pat<(v64i1 (bitconvert FR64X:$src)),
+          (KMOVQkr (VMOVSDto64Zrr FR64X:$src))>;
+def : Pat<(f64 (bitconvert VK64:$src)),
+          (VMOV64toSDZrr (KMOVQrk VK64:$src))>;
+
 //===----------------------------------------------------------------------===//
 // AVX-512  MOVSS, MOVSD
 //===----------------------------------------------------------------------===//

diff  --git a/llvm/test/CodeGen/X86/avx512bw-mask-op.ll b/llvm/test/CodeGen/X86/avx512bw-mask-op.ll
index c6a2da131a05..dcdbb16293bd 100644
--- a/llvm/test/CodeGen/X86/avx512bw-mask-op.ll
+++ b/llvm/test/CodeGen/X86/avx512bw-mask-op.ll
@@ -238,3 +238,51 @@ define i64 @test_v64i1_mul(i64 %x, i64 %y) {
   %ret = bitcast <64 x i1> %m2 to i64
   ret i64 %ret
 }
+
+define <32 x i1> @bitcast_f32_to_v32i1(float %x) {
+; CHECK-LABEL: bitcast_f32_to_v32i1:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    vmovd %xmm0, %eax
+; CHECK-NEXT:    kmovd %eax, %k0
+; CHECK-NEXT:    vpmovm2b %k0, %ymm0
+; CHECK-NEXT:    retq
+  %a = bitcast float %x to <32 x i1>
+  ret <32 x i1> %a
+}
+
+define <64 x i1> @bitcast_f64_to_v64i1(double %x) {
+; CHECK-LABEL: bitcast_f64_to_v64i1:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    vmovq %xmm0, %rax
+; CHECK-NEXT:    kmovq %rax, %k0
+; CHECK-NEXT:    vpmovm2b %k0, %zmm0
+; CHECK-NEXT:    retq
+  %a = bitcast double %x to <64 x i1>
+  ret <64 x i1> %a
+}
+
+define float @bitcast_v32i1_to_f32(<32 x i1> %x) {
+; CHECK-LABEL: bitcast_v32i1_to_f32:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    vpsllw $7, %ymm0, %ymm0
+; CHECK-NEXT:    vpmovmskb %ymm0, %eax
+; CHECK-NEXT:    vmovd %eax, %xmm0
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+  %a = bitcast <32 x i1> %x to float
+  ret float %a
+}
+
+define double @bitcast_v64i1_to_f64(<64 x i1> %x) {
+; CHECK-LABEL: bitcast_v64i1_to_f64:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    vpsllw $7, %zmm0, %zmm0
+; CHECK-NEXT:    vpmovb2m %zmm0, %k0
+; CHECK-NEXT:    kmovq %k0, %rax
+; CHECK-NEXT:    vmovq %rax, %xmm0
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+  %a = bitcast <64 x i1> %x to double
+  ret double %a
+}
+