[PATCH] D72300: [DAGCombiner] reduce shuffle of concat of same vector

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D72300#1807837 <https://reviews.llvm.org/D72300#1807837>, @RKSimon wrote:

> Its fine to leave it where it is - LGTM cheers.


On 2nd look at more motivating patterns, I think we should move it into partitionShuffleOfConcats() and loosen the isShuffleMaskLegal() restriction, but I'll make that a follow-on with more tests.

That's because we have illegal vectors like this being produced for AVX1/2 targets:

  define <16 x i32> @concat_self_v4i32(<4 x i32> %x) {
    %t90 = shufflevector <4 x i32> %x, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
    %t91 = shufflevector <8 x i32> %t90, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    %s = shufflevector <16 x i32> %t91, <16 x i32> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
    ret <16 x i32> %s
  }

This patch won't fire as-is on that because the 512-bit vector requires an illegal shuffle mask for AVX1/2.


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