[PATCH] D72317: [mlir][VectorOps] Implement insert_strided_slice conversion

[Nicolas Vasilache via Phabricator via llvm-commits]

nicolasvasilache created this revision.
nicolasvasilache added reviewers: ftynse, rriddle.
Herald added subscribers: llvm-commits, lucyrfox, mgester, arpith-jacob, antiagainst, shauheen, burmako, jpienaar, mehdi_amini.
Herald added a project: LLVM.
nicolasvasilache added a reviewer: AlexEichenberger.

This diff implements the progressive lowering of insert_strided_slice.
Two cases appear:

1. when the source and dest vectors have different ranks, extract the dest

subvector at the proper offset and reduce to case 2.

2. when they have the same rank N: a. if the source and dest type are the same, the insertion is trivial: just forward the source b. otherwise, iterate over all N-1 D subvectors and create an extract/insert_strided_slice/insert replacement, reducing the problem to vecotrs of the same N-1 rank.

This combines properly with the other conversion patterns to lower all the way to LLVM.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D72317

Files:
  mlir/include/mlir/IR/Attributes.h
  mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
  mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir

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