[PATCH] D72075: [ARM] Use correct TRAP opcode for thumb in FastISel

[Dave Green via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG0eb981b8ce70: [ARM] Use correct TRAP opcode for thumb in FastISel (authored by dmgreen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72075/new/

https://reviews.llvm.org/D72075

Files:
  llvm/lib/Target/ARM/ARMFastISel.cpp
  llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir


Index: llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir
===================================================================
--- llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir
+++ llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir
@@ -30,4 +30,4 @@
     renamable $r1 = tLDRi renamable $r4, 1, 14, $noreg :: (load 4)
   bb.2:
     liveins: $r4
-    TRAP
+    tTRAP
Index: llvm/lib/Target/ARM/ARMFastISel.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMFastISel.cpp
+++ llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -2566,8 +2566,12 @@
     return SelectCall(&I, "memset");
   }
   case Intrinsic::trap: {
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
-      Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
+    unsigned Opcode;
+    if (Subtarget->isThumb())
+      Opcode = ARM::tTRAP;
+    else
+      Opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode));
     return true;
   }
   }


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