[llvm] 0eb981b - [ARM] Use correct TRAP opcode for thumb in FastISel

[David Green via llvm-commits]

Author: David Green
Date: 2020-01-06T16:38:49Z
New Revision: 0eb981b8ce70d07b1b1fb39b969a6fe9509840c1

URL: https://github.com/llvm/llvm-project/commit/0eb981b8ce70d07b1b1fb39b969a6fe9509840c1
DIFF: https://github.com/llvm/llvm-project/commit/0eb981b8ce70d07b1b1fb39b969a6fe9509840c1.diff

LOG: [ARM] Use correct TRAP opcode for thumb in FastISel

We were previously unconditionally using the ARM::TRAP opcode, even
under Thumb. My understanding is that these are essentially the same
thing (they both result in a trap under Thumb), but the ARM::TRAP opcode
is marked as requiring IsARM, so it is more correct to use ARM::tTRAP.

Differential Revision: https://reviews.llvm.org/D72075

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMFastISel.cpp
    llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index 6c204bc0ed53..6e19db3c7e22 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -2566,8 +2566,12 @@ bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
     return SelectCall(&I, "memset");
   }
   case Intrinsic::trap: {
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
-      Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
+    unsigned Opcode;
+    if (Subtarget->isThumb())
+      Opcode = ARM::tTRAP;
+    else
+      Opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode));
     return true;
   }
   }

diff  --git a/llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir b/llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir
index 7a4db88479ba..4ebc0eeae328 100644
--- a/llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir
+++ b/llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir
@@ -30,4 +30,4 @@ body: |
     renamable $r1 = tLDRi renamable $r4, 1, 14, $noreg :: (load 4)
   bb.2:
     liveins: $r4
-    TRAP
+    tTRAP