[llvm] d68904f - [NFC] Fix trivial typos in comments
James Henderson via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 6 02:53:49 PST 2020
Author: James Henderson
Date: 2020-01-06T10:50:26Z
New Revision: d68904f957ae1f9b2309bdbf34258387c045ce27
URL: https://github.com/llvm/llvm-project/commit/d68904f957ae1f9b2309bdbf34258387c045ce27
DIFF: https://github.com/llvm/llvm-project/commit/d68904f957ae1f9b2309bdbf34258387c045ce27.diff
LOG: [NFC] Fix trivial typos in comments
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D72143
Patch by Kazuaki Ishizaki.
Added:
Modified:
llvm/bindings/ocaml/llvm/llvm.mli
llvm/include/llvm/ADT/PointerUnion.h
llvm/include/llvm/Analysis/ValueTracking.h
llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h
llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h
llvm/include/llvm/ExecutionEngine/Orc/OrcABISupport.h
llvm/include/llvm/IR/InstrTypes.h
llvm/include/llvm/Support/Allocator.h
llvm/include/llvm/Target/Target.td
llvm/include/llvm/Transforms/IPO/Attributor.h
llvm/lib/Bitcode/Reader/MetadataLoader.cpp
llvm/lib/CodeGen/Analysis.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
llvm/lib/MC/MCAssembler.cpp
llvm/lib/MC/MCExpr.cpp
llvm/lib/MC/MCParser/COFFAsmParser.cpp
llvm/lib/ProfileData/GCOV.cpp
llvm/lib/Target/AArch64/AArch64CallLowering.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp
llvm/lib/Target/ARM/ARMCallingConv.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
llvm/lib/Target/Mips/MipsInstrFPU.td
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/lib/Target/X86/X86InstrAVX512.td
llvm/lib/Transforms/IPO/Attributor.cpp
llvm/lib/Transforms/IPO/PartialInlining.cpp
llvm/lib/Transforms/Utils/AddDiscriminators.cpp
llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll
llvm/test/CodeGen/X86/DynamicCalleeSavedRegisters.ll
llvm/test/CodeGen/X86/lea.ll
llvm/test/CodeGen/X86/masked_gather_scatter.ll
llvm/test/CodeGen/X86/swifterror.ll
llvm/test/LTO/X86/parallel.ll
llvm/test/MC/AArch64/arm64-directive_loh.s
llvm/test/MC/ARM/misaligned-blx.s
llvm/test/Transforms/DeadArgElim/naked_functions.ll
llvm/test/Transforms/SCCP/apint-basictest3.ll
llvm/test/Transforms/SLPVectorizer/X86/align.ll
llvm/tools/llvm-c-test/echo.cpp
llvm/tools/llvm-objdump/MachODump.cpp
llvm/unittests/Analysis/VectorFunctionABITest.cpp
llvm/unittests/Analysis/VectorUtilsTest.cpp
llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp
llvm/utils/TableGen/CodeGenTarget.cpp
llvm/utils/TableGen/CodeGenTarget.h
llvm/utils/bugpoint/RemoteRunSafely.sh
Removed:
################################################################################
diff --git a/llvm/bindings/ocaml/llvm/llvm.mli b/llvm/bindings/ocaml/llvm/llvm.mli
index 48e099faf100..04e27438a479 100644
--- a/llvm/bindings/ocaml/llvm/llvm.mli
+++ b/llvm/bindings/ocaml/llvm/llvm.mli
@@ -1295,7 +1295,7 @@ val const_shufflevector : llvalue -> llvalue -> llvalue -> llvalue
val const_extractvalue : llvalue -> int array -> llvalue
(** [const_insertvalue agg val idxs] inserts the value [val] in the specified
- indexs [idxs] in the aggegate [agg]. Each [idxs] must be less than the size
+ indexs [idxs] in the aggregate [agg]. Each [idxs] must be less than the size
of the aggregate. See the method [llvm::ConstantExpr::getInsertValue]. *)
val const_insertvalue : llvalue -> llvalue -> int array -> llvalue
diff --git a/llvm/include/llvm/ADT/PointerUnion.h b/llvm/include/llvm/ADT/PointerUnion.h
index 98c905775a77..2ad96c52751d 100644
--- a/llvm/include/llvm/ADT/PointerUnion.h
+++ b/llvm/include/llvm/ADT/PointerUnion.h
@@ -93,7 +93,7 @@ namespace pointer_union_detail {
static constexpr int NumLowBitsAvailable = lowBitsAvailable<PTs...>();
};
- /// Implement assigment in terms of construction.
+ /// Implement assignment in terms of construction.
template <typename Derived, typename T> struct AssignableFrom {
Derived &operator=(T t) {
return static_cast<Derived &>(*this) = Derived(t);
diff --git a/llvm/include/llvm/Analysis/ValueTracking.h b/llvm/include/llvm/Analysis/ValueTracking.h
index 138037985986..89cf9abdc8ba 100644
--- a/llvm/include/llvm/Analysis/ValueTracking.h
+++ b/llvm/include/llvm/Analysis/ValueTracking.h
@@ -232,9 +232,9 @@ class Value;
/// return undef.
Value *isBytewiseValue(Value *V, const DataLayout &DL);
- /// Given an aggregrate and an sequence of indices, see if the scalar value
+ /// Given an aggregate and an sequence of indices, see if the scalar value
/// indexed is already around as a register, for example if it were inserted
- /// directly into the aggregrate.
+ /// directly into the aggregate.
///
/// If InsertBefore is not null, this function will duplicate (modified)
/// insertvalues when a part of a nested struct is extracted.
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
index 4901a3748e4a..bc9774e09acf 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
@@ -107,7 +107,7 @@ class CallLowering {
/// make these decisions: function formal arguments, call
/// instruction args, call instruction returns and function
/// returns. However, once a decision has been made on where an
- /// arugment should go, exactly what happens can vary slightly. This
+ /// argument should go, exactly what happens can vary slightly. This
/// class abstracts the
diff erences.
struct ValueHandler {
ValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
diff --git a/llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h b/llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h
index 1f686666c05f..893cfc1eb07c 100644
--- a/llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h
+++ b/llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h
@@ -32,7 +32,7 @@ class GsymReader;
/// The function information gets the function start address as an argument
/// to the FunctionInfo::decode(...) function. This information is calculated
/// from the GSYM header and an address offset from the GSYM address offsets
-/// table. The encoded FunctionInfo information must be alinged to a 4 byte
+/// table. The encoded FunctionInfo information must be aligned to a 4 byte
/// boundary.
///
/// The encoded data for a FunctionInfo starts with fixed data that all
diff --git a/llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h b/llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h
index 12c8187132ba..e61eb678c82e 100644
--- a/llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h
+++ b/llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h
@@ -82,15 +82,15 @@ class FileWriter;
/// The resulting GSYM size is smaller and causes fewer pages to be touched
/// during address lookups when the address table is smaller. The size of the
/// address offsets in the address table is specified in the header in
-/// Header.AddrOffSize. The first offset in the address table is alinged to
-/// Header.AddrOffSize alignement to ensure efficient access when loaded into
+/// Header.AddrOffSize. The first offset in the address table is aligned to
+/// Header.AddrOffSize alignment to ensure efficient access when loaded into
/// memory.
///
/// FUNCTION INFO OFFSETS TABLE
///
/// The function info offsets table immediately follows the address table and
/// consists of Header.NumAddresses 32 bit file offsets: one for each address
-/// in the address table. This data is algined to a 4 byte boundary. The
+/// in the address table. This data is aligned to a 4 byte boundary. The
/// offsets in this table are the relative offsets from the start offset of the
/// GSYM header and point to the function info data for each address in the
/// address table. Keeping this data separate from the address table helps to
diff --git a/llvm/include/llvm/ExecutionEngine/Orc/OrcABISupport.h b/llvm/include/llvm/ExecutionEngine/Orc/OrcABISupport.h
index 6a23bf3d0cd4..2e58ddd75d31 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/OrcABISupport.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/OrcABISupport.h
@@ -29,7 +29,7 @@ namespace orc {
/// Generic ORC ABI support.
///
-/// This class can be substituted as the target architecure support class for
+/// This class can be substituted as the target architecture support class for
/// ORC templates that require one (e.g. IndirectStubsManagers). It does not
/// support lazy JITing however, and any attempt to use that functionality
/// will result in execution of an llvm_unreachable.
diff --git a/llvm/include/llvm/IR/InstrTypes.h b/llvm/include/llvm/IR/InstrTypes.h
index 49f8ffddcabf..b2cdd58a5046 100644
--- a/llvm/include/llvm/IR/InstrTypes.h
+++ b/llvm/include/llvm/IR/InstrTypes.h
@@ -1947,7 +1947,7 @@ class CallBase : public Instruction {
/// Is the function attribute S disallowed by some operand bundle on
/// this operand bundle user?
bool isFnAttrDisallowedByOpBundle(StringRef S) const {
- // Operand bundles only possibly disallow readnone, readonly and argmenonly
+ // Operand bundles only possibly disallow readnone, readonly and argmemonly
// attributes. All String attributes are fine.
return false;
}
diff --git a/llvm/include/llvm/Support/Allocator.h b/llvm/include/llvm/Support/Allocator.h
index 106b90c35bf5..670335ffecbc 100644
--- a/llvm/include/llvm/Support/Allocator.h
+++ b/llvm/include/llvm/Support/Allocator.h
@@ -269,7 +269,7 @@ class BumpPtrAllocatorImpl
inline LLVM_ATTRIBUTE_RETURNS_NONNULL LLVM_ATTRIBUTE_RETURNS_NOALIAS void *
Allocate(size_t Size, size_t Alignment) {
- assert(Alignment > 0 && "0-byte alignnment is not allowed. Use 1 instead.");
+ assert(Alignment > 0 && "0-byte alignment is not allowed. Use 1 instead.");
return Allocate(Size, Align(Alignment));
}
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index c68977cf549e..321655d06b8e 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -1292,7 +1292,7 @@ class AsmParser {
// ReportMultipleNearMisses -
// When 0, the assembly matcher reports an error for one encoding or operand
// that did not match the parsed instruction.
- // When 1, the assmebly matcher returns a list of encodings that were close
+ // When 1, the assembly matcher returns a list of encodings that were close
// to matching the parsed instruction, so to allow more detailed error
// messages.
bit ReportMultipleNearMisses = 0;
diff --git a/llvm/include/llvm/Transforms/IPO/Attributor.h b/llvm/include/llvm/Transforms/IPO/Attributor.h
index 1aafab028bae..53236b54ff0f 100644
--- a/llvm/include/llvm/Transforms/IPO/Attributor.h
+++ b/llvm/include/llvm/Transforms/IPO/Attributor.h
@@ -283,7 +283,7 @@ struct IRPosition {
Argument *getAssociatedArgument() const;
/// Return true if the position refers to a function interface, that is the
- /// function scope, the function return, or an argumnt.
+ /// function scope, the function return, or an argument.
bool isFnInterfaceKind() const {
switch (getPositionKind()) {
case IRPosition::IRP_FUNCTION:
@@ -510,7 +510,7 @@ template <> struct DenseMapInfo<IRPosition> {
/// - the argument of the callee (IRP_ARGUMENT), if known
/// - the callee (IRP_FUNCTION), if known
/// - the position the call site argument is associated with if it is not
-/// anchored to the call site, e.g., if it is an arugment then the argument
+/// anchored to the call site, e.g., if it is an argument then the argument
/// (IRP_ARGUMENT)
class SubsumingPositionIterator {
SmallVector<IRPosition, 4> IRPositions;
@@ -2170,7 +2170,7 @@ struct AAAlign : public IRAttribute<
/// Return assumed alignment.
unsigned getAssumedAlign() const { return getAssumed(); }
- /// Return known alignemnt.
+ /// Return known alignment.
unsigned getKnownAlign() const { return getKnown(); }
/// Create an abstract attribute view for the position \p IRP.
diff --git a/llvm/lib/Bitcode/Reader/MetadataLoader.cpp b/llvm/lib/Bitcode/Reader/MetadataLoader.cpp
index 4da51dda8b74..d16c3b0ff59d 100644
--- a/llvm/lib/Bitcode/Reader/MetadataLoader.cpp
+++ b/llvm/lib/Bitcode/Reader/MetadataLoader.cpp
@@ -411,7 +411,7 @@ void PlaceholderQueue::flush(BitcodeReaderMetadataList &MetadataList) {
}
}
-} // anonynous namespace
+} // anonymous namespace
static Error error(const Twine &Message) {
return make_error<StringError>(
diff --git a/llvm/lib/CodeGen/Analysis.cpp b/llvm/lib/CodeGen/Analysis.cpp
index 4b738ca0e94d..1632895fe5fa 100644
--- a/llvm/lib/CodeGen/Analysis.cpp
+++ b/llvm/lib/CodeGen/Analysis.cpp
@@ -262,7 +262,7 @@ static bool isNoopBitcast(Type *T1, Type *T2,
/// Look through operations that will be free to find the earliest source of
/// this value.
///
-/// @param ValLoc If V has aggegate type, we will be interested in a particular
+/// @param ValLoc If V has aggregate type, we will be interested in a particular
/// scalar component. This records its address; the reverse of this list gives a
/// sequence of indices appropriate for an extractvalue to locate the important
/// value. This value is updated during the function and on exit will indicate
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 463c7a6bbee0..91b29e5270ca 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -620,7 +620,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
assert(NVT == ExtPassThru.getValueType() &&
- "Gather result type and the passThru agrument type should be the same");
+ "Gather result type and the passThru argument type should be the same");
SDLoc dl(N);
SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 4fa007710da9..00b05c5db2f8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4428,7 +4428,7 @@ static bool getUniformBase(const Value *&Ptr, SDValue &Base, SDValue &Index,
void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
SDLoc sdl = getCurSDLoc();
- // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
+ // llvm.masked.scatter.*(Src0, Ptrs, alignment, Mask)
const Value *Ptr = I.getArgOperand(1);
SDValue Src0 = getValue(I.getArgOperand(0));
SDValue Mask = getValue(I.getArgOperand(3));
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index ea971809d4e4..2b1ffab74b6f 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1287,7 +1287,7 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi,
bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist);
// If the instruction is convertible to 3 Addr, instead
- // of returning try 3 Addr transformation aggresively and
+ // of returning try 3 Addr transformation aggressively and
// use this variable to check later. Because it might be better.
// For example, we can just use `leal (%rsi,%rdi), %eax` and `ret`
// instead of the following code.
diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
index 51535e88285b..93b60f1e504f 100644
--- a/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
+++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
@@ -39,7 +39,7 @@ struct ContentDescriptor {
using ContentDescriptors = SmallVector<ContentDescriptor, 4>;
-} // end anonmyous namespace
+} // end anonymous namespace
void DWARFDebugLine::ContentTypeTracker::trackContentType(
dwarf::LineNumberEntryFormat ContentType) {
diff --git a/llvm/lib/MC/MCAssembler.cpp b/llvm/lib/MC/MCAssembler.cpp
index 332d93bd4d7d..4a8421299f65 100644
--- a/llvm/lib/MC/MCAssembler.cpp
+++ b/llvm/lib/MC/MCAssembler.cpp
@@ -951,7 +951,7 @@ bool MCAssembler::relaxLEB(MCAsmLayout &Layout, MCLEBFragment &LF) {
///
/// \param StartAddr start address of the fused/unfused branch.
/// \param Size size of the fused/unfused branch.
-/// \param BoundaryAlignment aligment requirement of the branch.
+/// \param BoundaryAlignment alignment requirement of the branch.
/// \returns true if the branch cross the boundary.
static bool mayCrossBoundary(uint64_t StartAddr, uint64_t Size,
Align BoundaryAlignment) {
@@ -964,7 +964,7 @@ static bool mayCrossBoundary(uint64_t StartAddr, uint64_t Size,
///
/// \param StartAddr start address of the fused/unfused branch.
/// \param Size size of the fused/unfused branch.
-/// \param BoundaryAlignment aligment requirement of the branch.
+/// \param BoundaryAlignment alignment requirement of the branch.
/// \returns true if the branch is against the boundary.
static bool isAgainstBoundary(uint64_t StartAddr, uint64_t Size,
Align BoundaryAlignment) {
@@ -976,7 +976,7 @@ static bool isAgainstBoundary(uint64_t StartAddr, uint64_t Size,
///
/// \param StartAddr start address of the fused/unfused branch.
/// \param Size size of the fused/unfused branch.
-/// \param BoundaryAlignment aligment requirement of the branch.
+/// \param BoundaryAlignment alignment requirement of the branch.
/// \returns true if the branch needs padding.
static bool needPadding(uint64_t StartAddr, uint64_t Size,
Align BoundaryAlignment) {
diff --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp
index 813c00f6f3bb..7f25fd4e90a7 100644
--- a/llvm/lib/MC/MCExpr.cpp
+++ b/llvm/lib/MC/MCExpr.cpp
@@ -601,7 +601,7 @@ static bool canFold(const MCAssembler *Asm, const MCSymbolRefExpr *A,
/// and
/// Result = (LHS_A - LHS_B + LHS_Cst) + (RHS_A - RHS_B + RHS_Cst).
///
-/// This routine attempts to aggresively fold the operands such that the result
+/// This routine attempts to aggressively fold the operands such that the result
/// is representable in an MCValue, but may not always succeed.
///
/// \returns True on success, false if the result is not representable in an
diff --git a/llvm/lib/MC/MCParser/COFFAsmParser.cpp b/llvm/lib/MC/MCParser/COFFAsmParser.cpp
index 06f8310ae061..51bb1fe92b73 100644
--- a/llvm/lib/MC/MCParser/COFFAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/COFFAsmParser.cpp
@@ -144,7 +144,7 @@ class COFFAsmParser : public MCAsmParserExtension {
COFFAsmParser() = default;
};
-} // end annonomous namespace.
+} // end anonymous namespace.
static SectionKind computeSectionKind(unsigned Flags) {
if (Flags & COFF::IMAGE_SCN_MEM_EXECUTE)
diff --git a/llvm/lib/ProfileData/GCOV.cpp b/llvm/lib/ProfileData/GCOV.cpp
index 00e6294c57a6..228c1b3b442a 100644
--- a/llvm/lib/ProfileData/GCOV.cpp
+++ b/llvm/lib/ProfileData/GCOV.cpp
@@ -439,7 +439,7 @@ LLVM_DUMP_METHOD void GCOVBlock::dump() const { print(dbgs()); }
//===----------------------------------------------------------------------===//
// Cycles detection
//
-// The algorithm in GCC is based on the algorihtm by Hawick & James:
+// The algorithm in GCC is based on the algorithm by Hawick & James:
// "Enumerating Circuits and Loops in Graphs with Self-Arcs and Multiple-Arcs"
// http://complexity.massey.ac.nz/cstn/013/cstn-013.pdf.
diff --git a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
index 2b5845dbcfb2..76ff238234d9 100644
--- a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
@@ -1000,7 +1000,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
0));
// Finally we can copy the returned value back into its virtual-register. In
- // symmetry with the arugments, the physical register must be an
+ // symmetry with the arguments, the physical register must be an
// implicit-define of the call instruction.
if (!Info.OrigRet.Ty->isVoidTy()) {
CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv);
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index b92ae1dbc5c6..f52feab03953 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -481,7 +481,7 @@ def QQQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqQuads)> {
// Vector operand versions of the FP registers. Alternate name printing and
-// assmebler matching.
+// assembler matching.
def VectorReg64AsmOperand : AsmOperandClass {
let Name = "VectorReg64";
let PredicateMethod = "isNeonVectorReg";
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 72526cac113e..42a667b67bfe 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -1,4 +1,4 @@
-//===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer -------------------===//
+//===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer --------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
diff --git a/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp b/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp
index b29cd75f75cf..ed23c8ea814b 100644
--- a/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp
@@ -1,4 +1,4 @@
-//===-- R600AsmPrinter.cpp - R600 Assebly printer ------------------------===//
+//===-- R600AsmPrinter.cpp - R600 Assembly printer ------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
diff --git a/llvm/lib/Target/ARM/ARMCallingConv.cpp b/llvm/lib/Target/ARM/ARMCallingConv.cpp
index 461de14da2e5..a47c59512592 100644
--- a/llvm/lib/Target/ARM/ARMCallingConv.cpp
+++ b/llvm/lib/Target/ARM/ARMCallingConv.cpp
@@ -181,7 +181,7 @@ static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned ValNo, MVT ValVT,
assert(PendingMembers[0].getLocVT() == LocVT);
// Add the argument to the list to be allocated once we know the size of the
- // aggregate. Store the type's required alignmnent as extra info for later: in
+ // aggregate. Store the type's required alignment as extra info for later: in
// the [N x i64] case all trace has been removed by the time we actually get
// to do allocation.
PendingMembers.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo,
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 1ee4e43398c4..1d7aae1aa409 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -14715,7 +14715,7 @@ bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned,
if (!VT.isSimple())
return false;
- // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
+ // The AllowsUnaligned flag models the SCTLR.A setting in ARM cpus
bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
auto Ty = VT.getSimpleVT().SimpleTy;
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 72b2feb6fbb9..28b11ad3f1aa 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -6703,7 +6703,7 @@ static void applyMnemonicAliases(StringRef &Mnemonic,
// omitted. We don't have a way to do that in tablegen, so fix it up here.
//
// We have to be careful to not emit an invalid Rt2 here, because the rest of
-// the assmebly parser could then generate confusing diagnostics refering to
+// the assembly parser could then generate confusing diagnostics refering to
// it. If we do find anything that prevents us from doing the transformation we
// bail out, and let the assembly parser report an error on the instruction as
// it is written.
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
index 38667d686b85..a9460b70da56 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
//
-// This file implements the unwind opcode assmebler for ARM exception handling
+// This file implements the unwind opcode assembler for ARM exception handling
// table.
//
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
index c3134c04b33a..5fb7307159d1 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
//
-// This file declares the unwind opcode assmebler for ARM exception handling
+// This file declares the unwind opcode assembler for ARM exception handling
// table.
//
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
index f12189052699..c23b837bb62f 100644
--- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
@@ -119,7 +119,7 @@ let Namespace = "Hexagon" in {
def P2 : Rp<2, "p2">, DwarfRegNum<[65]>;
def P3 : Rp<3, "p3">, DwarfRegNum<[66]>;
- // Fake register to represent USR.OVF bit. Artihmetic/saturating instruc-
+ // Fake register to represent USR.OVF bit. Arithmetic/saturating instruc-
// tions modify this bit, and multiple such instructions are allowed in the
// same packet. We need to ignore output dependencies on this bit, but not
// on the entire USR.
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td
index 5a01e3480031..79776998463f 100644
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@@ -628,7 +628,7 @@ let AdditionalPredicates = [IsNotNaCl, NotInMicroMips],
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
}
-/// Floating-point Aritmetic
+/// Floating-point Arithmetic
let AdditionalPredicates = [NotInMicroMips] in {
def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
ADDS_FM<0x00, 16>, ISA_MIPS1;
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 032e3a920637..01b97ba6ab20 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -380,7 +380,7 @@ bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) co
// This is eiher:
// 1) A fixed frame index object which we know are aligned so
// as long as we have a valid DForm/DSForm/DQForm (non XForm) we don't
- // need to consider the alignement here.
+ // need to consider the alignment here.
// 2) A not fixed object but in that case we now know that the min required
// alignment is no more than 1 based on the previous check.
if (InstrInfo->isXFormMemOp(Opcode))
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 5cf71c25b9bf..0b263acbc95e 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -9621,7 +9621,7 @@ defm : AVX512_pmovx_patterns<"VPMOVSX", sext, sext_invec>;
defm : AVX512_pmovx_patterns<"VPMOVZX", zext, zext_invec>;
// Without BWI we can't do a trunc from v16i16 to v16i8. DAG combine can merge
-// ext+trunc aggresively making it impossible to legalize the DAG to this
+// ext+trunc aggressively making it impossible to legalize the DAG to this
// pattern directly.
let Predicates = [HasAVX512, NoBWI] in {
def: Pat<(v16i8 (trunc (v16i16 VR256X:$src))),
diff --git a/llvm/lib/Transforms/IPO/Attributor.cpp b/llvm/lib/Transforms/IPO/Attributor.cpp
index ef52775c759d..13fcf6aa7247 100644
--- a/llvm/lib/Transforms/IPO/Attributor.cpp
+++ b/llvm/lib/Transforms/IPO/Attributor.cpp
@@ -154,7 +154,7 @@ static cl::opt<bool> DisableAttributor(
static cl::opt<bool> AnnotateDeclarationCallSites(
"attributor-annotate-decl-cs", cl::Hidden,
- cl::desc("Annoate call sites of function declarations."), cl::init(false));
+ cl::desc("Annotate call sites of function declarations."), cl::init(false));
static cl::opt<bool> ManifestInternal(
"attributor-manifest-internal", cl::Hidden,
@@ -3544,7 +3544,7 @@ struct AAAlignImpl : AAAlign {
if (SI->getPointerOperand() == &AnchorVal)
if (SI->getAlignment() < getAssumedAlign()) {
STATS_DECLTRACK(AAAlign, Store,
- "Number of times alignemnt added to a store");
+ "Number of times alignment added to a store");
SI->setAlignment(Align(getAssumedAlign()));
Changed = ChangeStatus::CHANGED;
}
@@ -3553,7 +3553,7 @@ struct AAAlignImpl : AAAlign {
if (LI->getAlignment() < getAssumedAlign()) {
LI->setAlignment(Align(getAssumedAlign()));
STATS_DECLTRACK(AAAlign, Load,
- "Number of times alignemnt added to a load");
+ "Number of times alignment added to a load");
Changed = ChangeStatus::CHANGED;
}
}
diff --git a/llvm/lib/Transforms/IPO/PartialInlining.cpp b/llvm/lib/Transforms/IPO/PartialInlining.cpp
index 4408c34d13af..cd3701e90308 100644
--- a/llvm/lib/Transforms/IPO/PartialInlining.cpp
+++ b/llvm/lib/Transforms/IPO/PartialInlining.cpp
@@ -702,7 +702,7 @@ PartialInlinerImpl::computeOutliningInfo(Function *F) {
return OutliningInfo;
}
-// Check if there is PGO data or user annoated branch data:
+// Check if there is PGO data or user annotated branch data:
static bool hasProfileData(Function *F, FunctionOutliningInfo *OI) {
if (F->hasProfileData())
return true;
diff --git a/llvm/lib/Transforms/Utils/AddDiscriminators.cpp b/llvm/lib/Transforms/Utils/AddDiscriminators.cpp
index d58e6eb26ff3..0908b361a4d4 100644
--- a/llvm/lib/Transforms/Utils/AddDiscriminators.cpp
+++ b/llvm/lib/Transforms/Utils/AddDiscriminators.cpp
@@ -233,7 +233,7 @@ static bool addDiscriminators(Function &F) {
LocationSet CallLocations;
for (auto &I : B.getInstList()) {
// We bypass intrinsic calls for the following two reasons:
- // 1) We want to avoid a non-deterministic assigment of
+ // 1) We want to avoid a non-deterministic assignment of
// discriminators.
// 2) We want to minimize the number of base discriminators used.
if (!isa<InvokeInst>(I) && (!isa<CallInst>(I) || isa<IntrinsicInst>(I)))
diff --git a/llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll b/llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll
index 9d3e18efea21..53d29e2ac3cf 100644
--- a/llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll
+++ b/llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll
@@ -1,5 +1,5 @@
; RUN: llc -mcpu=generic -mtriple=i386-apple-darwin -tailcallopt -enable-misched=false < %s | FileCheck %s
-; Check that lowered argumens do not overwrite the return address before it is moved.
+; Check that lowered arguments do not overwrite the return address before it is moved.
; Bug 6225
;
; If a call is a fastcc tail call and tail call optimization is enabled, the
diff --git a/llvm/test/CodeGen/X86/DynamicCalleeSavedRegisters.ll b/llvm/test/CodeGen/X86/DynamicCalleeSavedRegisters.ll
index 880ac5b006bc..75c44810551d 100644
--- a/llvm/test/CodeGen/X86/DynamicCalleeSavedRegisters.ll
+++ b/llvm/test/CodeGen/X86/DynamicCalleeSavedRegisters.ll
@@ -7,7 +7,7 @@ declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0);
; One might think that the caller could assume that ESI value is the same before
; and after calling the callee.
; However, RegCall also says that a register that was used for
-; passing/returning argumnets, can be assumed to be modified by the callee.
+; passing/returning arguments, can be assumed to be modified by the callee.
; In other words, it is no longer a callee saved register.
; In this case we want to see that EDX/ECX values are saved and EDI/ESI are assumed
; to be modified by the callee.
diff --git a/llvm/test/CodeGen/X86/lea.ll b/llvm/test/CodeGen/X86/lea.ll
index a326b1ef440e..33d121f6849b 100644
--- a/llvm/test/CodeGen/X86/lea.ll
+++ b/llvm/test/CodeGen/X86/lea.ll
@@ -23,7 +23,7 @@ define i32 @test1(i32 %x) nounwind {
; ISel the add of -4 with a neg and use an lea for the rest of the
-; arithemtic.
+; arithmetic.
define i32 @test2(i32 %x_offs) nounwind readnone {
; LINUX-LABEL: test2:
; LINUX: # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/X86/masked_gather_scatter.ll b/llvm/test/CodeGen/X86/masked_gather_scatter.ll
index 2e4edb990942..12309044e395 100644
--- a/llvm/test/CodeGen/X86/masked_gather_scatter.ll
+++ b/llvm/test/CodeGen/X86/masked_gather_scatter.ll
@@ -458,7 +458,7 @@ define <16 x i32> @test8(<16 x i32*> %ptr.random, <16 x i32> %ind, i16 %mask) {
%struct.RT = type { i8, [10 x [20 x i32]], i8 }
%struct.ST = type { i32, double, %struct.RT }
-; Masked gather for agregate types
+; Masked gather for aggregate types
; Test9 and Test10 should give the same result (scalar and vector indices in GEP)
diff --git a/llvm/test/CodeGen/X86/swifterror.ll b/llvm/test/CodeGen/X86/swifterror.ll
index c37322952097..1388c61c1898 100644
--- a/llvm/test/CodeGen/X86/swifterror.ll
+++ b/llvm/test/CodeGen/X86/swifterror.ll
@@ -533,7 +533,7 @@ define swiftcc void @swifterror_reg_clobber(%swift_error** nocapture %err) {
}
; CHECK-APPLE-LABEL: params_in_reg
-; Save callee save registers to store clobbered arugments.
+; Save callee save registers to store clobbered arguments.
; CHECK-APPLE: pushq %rbp
; CHECK-APPLE: pushq %r15
; CHECK-APPLE: pushq %r14
diff --git a/llvm/test/LTO/X86/parallel.ll b/llvm/test/LTO/X86/parallel.ll
index 9a8494c127f1..b3c128193821 100644
--- a/llvm/test/LTO/X86/parallel.ll
+++ b/llvm/test/LTO/X86/parallel.ll
@@ -3,7 +3,7 @@
; RUN: llvm-nm %t.o.0 | FileCheck --check-prefix=CHECK0 %s
; RUN: llvm-nm %t.o.1 | FileCheck --check-prefix=CHECK1 %s
-; FIXME: Investigate test failures on these architecures.
+; FIXME: Investigate test failures on these architectures.
; UNSUPPORTED: mips, mipsel, aarch64, powerpc64
target triple = "x86_64-unknown-linux-gnu"
diff --git a/llvm/test/MC/AArch64/arm64-directive_loh.s b/llvm/test/MC/AArch64/arm64-directive_loh.s
index 654dc9e70067..44f9539ba52e 100644
--- a/llvm/test/MC/AArch64/arm64-directive_loh.s
+++ b/llvm/test/MC/AArch64/arm64-directive_loh.s
@@ -84,13 +84,13 @@ _fct1:
# CHECK-ERRORS-NEXT: ^
.loh 1 L1, L2, L3
-# Too few argumets.
+# Too few arguments.
# CHECK-ERRORS: error: unexpected token in '.loh' directive
# CHECK-ERRORS-NEXT: .loh AdrpAdrp L1
# CHECK-ERRORS-NEXT: ^
.loh AdrpAdrp L1
-# Too few argumets with alternative syntax.
+# Too few arguments with alternative syntax.
# CHECK-ERRORS: error: unexpected token in '.loh' directive
# CHECK-ERRORS-NEXT: .loh 1 L1
# CHECK-ERRORS-NEXT: ^
diff --git a/llvm/test/MC/ARM/misaligned-blx.s b/llvm/test/MC/ARM/misaligned-blx.s
index b3cef0275280..f9250bf535ba 100644
--- a/llvm/test/MC/ARM/misaligned-blx.s
+++ b/llvm/test/MC/ARM/misaligned-blx.s
@@ -6,7 +6,7 @@
_f1:
bx lr
- @ A misalgined ARM destination.
+ @ A misaligned ARM destination.
.arm
.globl _misaligned
_misaligned:
diff --git a/llvm/test/Transforms/DeadArgElim/naked_functions.ll b/llvm/test/Transforms/DeadArgElim/naked_functions.ll
index b7955a10127d..ed125d45e517 100644
--- a/llvm/test/Transforms/DeadArgElim/naked_functions.ll
+++ b/llvm/test/Transforms/DeadArgElim/naked_functions.ll
@@ -1,6 +1,6 @@
; RUN: opt -S -deadargelim %s | FileCheck %s
-; Don't eliminate dead arugments from naked functions.
+; Don't eliminate dead arguments from naked functions.
; CHECK: define internal i32 @naked(i32 %x)
define internal i32 @naked(i32 %x) #0 {
diff --git a/llvm/test/Transforms/SCCP/apint-basictest3.ll b/llvm/test/Transforms/SCCP/apint-basictest3.ll
index b8fcca6fda93..863902c07d65 100644
--- a/llvm/test/Transforms/SCCP/apint-basictest3.ll
+++ b/llvm/test/Transforms/SCCP/apint-basictest3.ll
@@ -1,5 +1,5 @@
; This is a basic sanity check for constant propagation. It tests the basic
-; arithmatic operations.
+; arithmetic operations.
; RUN: opt < %s -sccp -S | not grep mul
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/align.ll b/llvm/test/Transforms/SLPVectorizer/X86/align.ll
index 5c7c4ceae817..c27890ca1691 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/align.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/align.ll
@@ -39,7 +39,7 @@ entry:
ret void
}
-; Float has 4 byte abi alignment on x86_64. We must use the alignmnet of the
+; Float has 4 byte abi alignment on x86_64. We must use the alignment of the
; value being loaded/stored not the alignment of the pointer type.
define void @test2(float * %a, float * %b) {
diff --git a/llvm/tools/llvm-c-test/echo.cpp b/llvm/tools/llvm-c-test/echo.cpp
index 7fca8ada5145..71b101596ee5 100644
--- a/llvm/tools/llvm-c-test/echo.cpp
+++ b/llvm/tools/llvm-c-test/echo.cpp
@@ -29,8 +29,8 @@ using namespace llvm;
template<typename T>
struct CAPIDenseMap {};
-// The default DenseMapInfo require to know about pointer alignement.
-// Because the C API uses opaques pointer types, their alignement is unknown.
+// The default DenseMapInfo require to know about pointer alignment.
+// Because the C API uses opaques pointer types, their alignment is unknown.
// As a result, we need to roll out our own implementation.
template<typename T>
struct CAPIDenseMap<T*> {
diff --git a/llvm/tools/llvm-objdump/MachODump.cpp b/llvm/tools/llvm-objdump/MachODump.cpp
index fc3503dd0ec8..3d8f3d9c5e91 100644
--- a/llvm/tools/llvm-objdump/MachODump.cpp
+++ b/llvm/tools/llvm-objdump/MachODump.cpp
@@ -7730,7 +7730,7 @@ static void DisassembleMachO(StringRef Filename, MachOObjectFile *MachOOF,
}
}
// The TripleName's need to be reset if we are called again for a
diff erent
- // archtecture.
+ // architecture.
TripleName = "";
ThumbTripleName = "";
diff --git a/llvm/unittests/Analysis/VectorFunctionABITest.cpp b/llvm/unittests/Analysis/VectorFunctionABITest.cpp
index 6aaa38c7d83a..fee7a5e33f14 100644
--- a/llvm/unittests/Analysis/VectorFunctionABITest.cpp
+++ b/llvm/unittests/Analysis/VectorFunctionABITest.cpp
@@ -256,7 +256,7 @@ TEST_F(VFABIParserTest, Align) {
EXPECT_EQ(Parameters.size(), (unsigned)1);
EXPECT_EQ(Parameters[0].Alignment, Align(2));
- // Missing alignement value.
+ // Missing alignment value.
EXPECT_FALSE(invokeParser("_ZGVsM2l2a_sin"));
// Invalid alignment token "x".
EXPECT_FALSE(invokeParser("_ZGVsM2l2ax_sin"));
diff --git a/llvm/unittests/Analysis/VectorUtilsTest.cpp b/llvm/unittests/Analysis/VectorUtilsTest.cpp
index 7a698f308220..074316082d18 100644
--- a/llvm/unittests/Analysis/VectorUtilsTest.cpp
+++ b/llvm/unittests/Analysis/VectorUtilsTest.cpp
@@ -433,7 +433,7 @@ TEST_F(VFShapeAPITest, Parameters_ValidOpenMPLinear) {
TEST_F(VFShapeAPITest, Parameters_Invalid) {
#ifndef NDEBUG
- // Wrong order is checked by an asseretion: make sure that the
+ // Wrong order is checked by an assertion: make sure that the
// assertion is not removed.
EXPECT_DEATH(validParams({{1, VFParamKind::Vector}}),
"Broken parameter list.");
diff --git a/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp b/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp
index 072742aab411..a8f6d883028d 100644
--- a/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp
+++ b/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp
@@ -1,4 +1,4 @@
-//=== WebAssemblyExceptionInfoTest.cpp - WebAssebmlyExceptionInfo unit tests =//
+//=== WebAssemblyExceptionInfoTest.cpp - WebAssemblyExceptionInfo unit tests =//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index fcfe6d124a8e..91253131ec9b 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -260,7 +260,7 @@ Record *CodeGenTarget::getAsmParser() const {
return LI[AsmParserNum];
}
-/// getAsmParserVariant - Return the AssmblyParserVariant definition for
+/// getAsmParserVariant - Return the AssemblyParserVariant definition for
/// this target.
///
Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
@@ -272,7 +272,7 @@ Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
return LI[i];
}
-/// getAsmParserVariantCount - Return the AssmblyParserVariant definition
+/// getAsmParserVariantCount - Return the AssemblyParserVariant definition
/// available for this target.
///
unsigned CodeGenTarget::getAsmParserVariantCount() const {
diff --git a/llvm/utils/TableGen/CodeGenTarget.h b/llvm/utils/TableGen/CodeGenTarget.h
index d52ffac4ce6c..6c89f34c50ec 100644
--- a/llvm/utils/TableGen/CodeGenTarget.h
+++ b/llvm/utils/TableGen/CodeGenTarget.h
@@ -86,12 +86,12 @@ class CodeGenTarget {
///
Record *getAsmParser() const;
- /// getAsmParserVariant - Return the AssmblyParserVariant definition for
+ /// getAsmParserVariant - Return the AssemblyParserVariant definition for
/// this target.
///
Record *getAsmParserVariant(unsigned i) const;
- /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
+ /// getAsmParserVariantCount - Return the AssemblyParserVariant definition
/// available for this target.
///
unsigned getAsmParserVariantCount() const;
diff --git a/llvm/utils/bugpoint/RemoteRunSafely.sh b/llvm/utils/bugpoint/RemoteRunSafely.sh
index f390e339ea9a..302c0db4e3fa 100644
--- a/llvm/utils/bugpoint/RemoteRunSafely.sh
+++ b/llvm/utils/bugpoint/RemoteRunSafely.sh
@@ -33,7 +33,7 @@ moreArgsExpected()
# $2 - number of arguments to shift
if [ $1 -lt $2 ]
then
- echo "Error: Wrong number of argumants."
+ echo "Error: Wrong number of arguments."
printUsageAndExit
fi
}
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