[PATCH] D70230: [DAGCombine] Don't check the legality of type when combine the SIGN_EXTEND_INREG
qshanz via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 5 19:11:55 PST 2020
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb9780f4f80ba: [DAGCombine] Don't check the legality of type when combine the SIGN_EXTEND_INREG (authored by steven.zhang).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D70230/new/
https://reviews.llvm.org/D70230
Files:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/PowerPC/sext-vector-inreg.ll
Index: llvm/test/CodeGen/PowerPC/sext-vector-inreg.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/sext-vector-inreg.ll
+++ llvm/test/CodeGen/PowerPC/sext-vector-inreg.ll
@@ -4,11 +4,8 @@
define <4 x i32> @test_signext_vector_inreg(<4 x i16> %n) {
; CHECK-P9-LABEL: test_signext_vector_inreg:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: vspltisw 3, 8
; CHECK-P9-NEXT: vmrglh 2, 2, 2
-; CHECK-P9-NEXT: vadduwm 3, 3, 3
-; CHECK-P9-NEXT: vslw 2, 2, 3
-; CHECK-P9-NEXT: vsraw 2, 2, 3
+; CHECK-P9-NEXT: vextsh2w 2, 2
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: test_signext_vector_inreg:
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7733,8 +7733,9 @@
if (VT.isVector())
ExtVT = EVT::getVectorVT(*DAG.getContext(),
ExtVT, VT.getVectorNumElements());
- if ((!LegalOperations ||
- TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
+ if (!LegalOperations ||
+ TLI.getOperationAction(ISD::SIGN_EXTEND_INREG, ExtVT) ==
+ TargetLowering::Legal)
return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
N0.getOperand(0), DAG.getValueType(ExtVT));
}
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