[PATCH] D72134: [RISCV] Fix test for inline asm z constraint modifier
Luís Marques via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 3 02:54:44 PST 2020
luismarques created this revision.
luismarques added reviewers: asb, lenary, jrtc27.
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Herald added a project: LLVM.
The inline assembly `z` constraint modifier is handled by the following code in `RISCVAsmPrinter.cpp`:
case 'z': // Print zero register if zero, regular printing otherwise.
if (MO.isImm() && MO.getImm() == 0) {
OS << RISCVInstPrinter::getRegisterName(RISCV::X0);
return false;
}
break;
Because the test was using an `r` operand constraint, the condition `MO.isImm()` wouldn't trigger, so we didn't actually have a test for the `z` modifier. The `zero` we were seeing in the test CHECK line was unrelated to the modifier, and would even persist if the modifier wasn't used.
This patch changes the relevant tests to use an `i` constraint, which does trigger the `z` constraint modifier handling code.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D72134
Files:
llvm/test/CodeGen/RISCV/inline-asm.ll
Index: llvm/test/CodeGen/RISCV/inline-asm.ll
===================================================================
--- llvm/test/CodeGen/RISCV/inline-asm.ll
+++ llvm/test/CodeGen/RISCV/inline-asm.ll
@@ -189,27 +189,25 @@
; RV64I-NEXT: add a0, a0, zero
; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret
- %1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,r"(i32 %a, i32 0)
+ %1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,i"(i32 %a, i32 0)
ret i32 %1
}
define i32 @modifier_z_nonzero(i32 %a) nounwind {
; RV32I-LABEL: modifier_z_nonzero:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi a1, zero, 1
; RV32I-NEXT: #APP
-; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: add a0, a0, 1
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret
;
; RV64I-LABEL: modifier_z_nonzero:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: #APP
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: add a0, a0, 1
; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret
- %1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,r"(i32 %a, i32 1)
+ %1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,i"(i32 %a, i32 1)
ret i32 %1
}
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