[PATCH] D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

[qshanz via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG2133d3c5586b: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for… (authored by steven.zhang).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70000/new/

https://reviews.llvm.org/D70000

Files:
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
  llvm/test/CodeGen/ARM/signext-inreg.ll
  llvm/test/CodeGen/Hexagon/signext-inreg.ll
  llvm/test/CodeGen/Thumb2/mve-sext.ll

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