[PATCH] D72118: Move tail call disabling code to target independent code

[Reid Kleckner via Phabricator via llvm-commits]

rnk created this revision.
rnk added reviewers: echristo, MaskRay.
Herald added subscribers: luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, jsji, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, kbarton, hiraditya, nhaehnle, jvesely, nemanjai, arsenm.
Herald added a project: LLVM.

When the "disable-tail-calls" attribute was added, checks were added for
it in various backends. Now this code has proliferated, and it is
something the target is responsible for checking. Move that
responsibility back to the ISels (fast, global, and SD).

There's no major functionality change, except for targets that never
implemented this check.

This LLVM attribute was originally added in
d9699bc7bdf0362173fcd256690f61a4d47429c2 (2015).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D72118

Files:
  llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
  llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/AArch64/tail-call.ll
  llvm/test/CodeGen/RISCV/tail-calls.ll

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