[PATCH] D72220: [X86] Support function attribute "patchable-function-entry"

[Fangrui Song via Phabricator via llvm-commits]

MaskRay created this revision.
MaskRay added reviewers: dberris, kristof.beyls, nickdesaulniers, rnk.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

For x86-64, we diverge from GCC -fpatchable-function-entry in that we
emit multi-byte NOPs.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D72220

Files:
  llvm/lib/Target/X86/X86MCInstLower.cpp
  llvm/test/CodeGen/X86/patchable-function-entry.ll


Index: llvm/test/CodeGen/X86/patchable-function-entry.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/patchable-function-entry.ll
@@ -0,0 +1,32 @@
+; RUN: llc -mtriple=i386 %s -o - | FileCheck --check-prefixes=CHECK,32 %s
+; RUN: llc -mtriple=x86_64 %s -o - | FileCheck --check-prefixes=CHECK,64 %s
+
+define void @f0() "patchable-function-entry"="0,0" {
+; CHECK-LABEL: f0:
+; CHECK-NOT:   nop
+; CHECK:       ret
+  ret void
+}
+
+define void @f1() "patchable-function-entry"="1,0" {
+; CHECK-LABEL: f1:
+; CHECK:       nop
+; CHECK-NEXT:  ret
+  ret void
+}
+
+define void @f3() "patchable-function-entry"="3,0" {
+; CHECK-LABEL: f3:
+; 32-COUNT-3:  nop
+; 64:          nopl (%rax)
+; CHECK:       ret
+  ret void
+}
+
+define void @f5() "patchable-function-entry"="5,0" {
+; CHECK-LABEL: f5:
+; 32-COUNT-5:  nop
+; 64:          nopl 8(%rax,%rax)
+; CHECK-NEXT:  ret
+  ret void
+}
Index: llvm/lib/Target/X86/X86MCInstLower.cpp
===================================================================
--- llvm/lib/Target/X86/X86MCInstLower.cpp
+++ llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -1033,9 +1033,11 @@
 /// bytes.  Return the size of nop emitted.
 static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
                         const MCSubtargetInfo &STI) {
-  // This works only for 64bit. For 32bit we have to do additional checking if
-  // the CPU supports multi-byte nops.
-  assert(Is64Bit && "EmitNops only supports X86-64");
+  if (!Is64Bit) {
+    // TODO Do additional checking if the CPU supports multi-byte nops.
+    OS.EmitInstruction(MCInstBuilder(X86::NOOP), STI);
+    return 1;
+  }
 
   unsigned NopSize;
   unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
@@ -1557,6 +1559,15 @@
 
 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
                                                   X86MCInstLower &MCIL) {
+  const Function &F = MF->getFunction();
+  if (F.hasFnAttribute("patchable-function-entry")) {
+    StringRef Entry = F.getFnAttribute("patchable-function-entry").getValueAsString();
+    unsigned Num;
+    if (Entry.consumeInteger(10, Num))
+      return;
+    EmitNops(*OutStreamer, Num, Subtarget->is64Bit(), getSubtargetInfo());
+    return;
+  }
   // We want to emit the following pattern:
   //
   //   .p2align 1, ...


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