[PATCH] D71929: AMDGPU/GlobalISel: Refine SMRD selection rules

[Matt Arsenault via Phabricator via llvm-commits]

arsenm marked an inline comment as done.
arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:414
+  // There are no extending SMRD/SMEM loads, and they require 4-byte alignment.
   return MMO->getSize() >= 4 && MMO->getAlignment() >= 4 &&
+    // Can't do a scalar atomic load.
----------------
rampitec wrote:
> '(MMO->getSize() % 4) == 0'? What if we need 6 bytes, like v3i16?
If it was legal, the alignment is high enough


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71929/new/

https://reviews.llvm.org/D71929