[PATCH] D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

[qshanz via Phabricator via llvm-commits]

steven.zhang updated this revision to Diff 235823.
steven.zhang added a comment.

Rebase the patch due to the AArch64 commit 65651f197a2c <https://reviews.llvm.org/rG65651f197a2c5a7b62f67619c169d2af616a81c6> which try to legalize sext_inreg for vector type for SVE. We need to specify it explicitly instead of relying on the default value. I will hold on this patch for several days in case someone has comments on the change of "SVE" part.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70000/new/

https://reviews.llvm.org/D70000

Files:
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
  llvm/test/CodeGen/ARM/signext-inreg.ll
  llvm/test/CodeGen/Hexagon/signext-inreg.ll
  llvm/test/CodeGen/Thumb2/mve-sext.ll

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