[PATCH] D72056: [RISCV] Generate PIC address sequence for medany -fno-pic

[James Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

I am still of the view that we should support rewriting the instruction stream in the linker when necessary like BFD does. We need to do this to be able to link in GCC-compiled code, including libraries. It is a very simple thing to do with a patch available that provides consistency between the GNU world and the LLVM world.



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Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:680
+  if (MF->getTarget().isPositionIndependent() ||
+      MF->getTarget().getCodeModel() != CodeModel::Small) {
     const auto &STI = MF->getSubtarget<RISCVSubtarget>();
----------------
This is confusing and differs from when you invoke the assembler manually, even via the Clang driver with the right code model specified. Any `la`s there will be assembled as `AUIPC`/`ADDI`. I am of the view it was a mistake to make `la`'s behaviour conditional on PICness and it should have always used the GOT, but this is what we have.


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Comment at: llvm/lib/Target/TargetMachine.cpp:192
       return false;
+    // RISC-V non-small code models prefer avoiding copy relocations.
+    if (TT.isRISCV() && getCodeModel() != CodeModel::Small)
----------------
Are we sure we want to do this and take the performance hit over GCC due to the extra level of indirection on every single extern global access? If this is the solution to take for extern weak, I think we should limit it to just that and have a separate discussion about non-extern-weak.


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  https://reviews.llvm.org/D72056/new/

https://reviews.llvm.org/D72056