[PATCH] D72031: [Scheduling] Create the missing dependency edges for store cluster

[qshanz via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: fhahn, evandro, arsenm, jsji, hfinkel, kbarton, PowerPC.
Herald added subscribers: javed.absar, hiraditya, tpr, nhaehnle, wdng, jvesely, MatzeB.
Herald added a project: LLVM.

If it is load cluster, we don't need to create the dependency edges from SUb to SUa as they both depend on the base register "reg"

       +-------+
  +---->  reg  |
  |    +---+---+
  |        ^
  |        |
  |        |
  |        |
  |    +---+---+
  |    |  SUa  |  Load 0(reg)
  |    +---+---+
  |        ^
  |        |
  |        |
  |    +---+---+
  +----+  SUb  |  Load 4(reg)
       +-------+

But if it is store cluster, we need to create it as follow shows to avoid the instruction store depend on scheduled in-between SUb and SUa. Notice that, AMDGPU several cases break due to this change and I examine them one by one, no obvious issue found from scheduling aspect. However, need double confirm. And one case show some deg in the final code sequence, which seems to be an issue of the later pass I think.

       +-------+
  +---->  reg  |
  |    +---+---+
  |        ^
  |        |         Missing       +-------+
  |        | +-------------------->+   y   |
  |        | |                     +---+---+
  |    +---+-+-+                       ^
  |    |  SUa  |  Store x 0(reg)       |
  |    +---+---+                       |
  |        ^                           |
  |        |  +------------------------+
  |        |  |
  |    +---+--++
  +----+  SUb  |  Store y 4(reg)
       +-------+


https://reviews.llvm.org/D72031

Files:
  llvm/lib/CodeGen/MachineScheduler.cpp
  llvm/test/CodeGen/AArch64/macro-fusion.ll
  llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll
  llvm/test/CodeGen/AMDGPU/max.i16.ll
  llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
  llvm/test/CodeGen/AMDGPU/scratch-simple.ll

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