[llvm] fcbf05b - [PowerPC][NFC] Fix clang-tidy warning

[Jinsong Ji via llvm-commits]

Author: Jinsong Ji
Date: 2019-12-31T16:24:40Z
New Revision: fcbf05bbdccc8a32f6a80316ea1c13be7e7eeae2

URL: https://github.com/llvm/llvm-project/commit/fcbf05bbdccc8a32f6a80316ea1c13be7e7eeae2
DIFF: https://github.com/llvm/llvm-project/commit/fcbf05bbdccc8a32f6a80316ea1c13be7e7eeae2.diff

LOG: [PowerPC][NFC] Fix clang-tidy warning

Reported by
https://results.llvm-merge-guard.org/amd64_debian_testing_clang8-726/clang-tidy.txt

/mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/llvm/lib/Target/PowerPC/PPCISelLowering.cpp:11672:10:
warning: invalid case style for variable 'isEQ'
[readability-identifier-naming]
    bool isEQ = (MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT ||
         ^~~~
         IsEq
/mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/llvm/lib/Target/PowerPC/PPCISelLowering.cpp:11679:14:
warning: invalid case style for variable 'dl'
[readability-identifier-naming]
    DebugLoc dl = MI.getDebugLoc();
             ^~
             Dl

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index cbbf13246205..9fab29dded75 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11669,20 +11669,20 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                        MI.getOpcode() == PPC::ANDIo_1_GT_BIT8)
                           ? PPC::ANDI8o
                           : PPC::ANDIo;
-    bool isEQ = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
+    bool IsEQ = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
                  MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8);
 
     MachineRegisterInfo &RegInfo = F->getRegInfo();
     Register Dest = RegInfo.createVirtualRegister(
         Opcode == PPC::ANDIo ? &PPC::GPRCRegClass : &PPC::G8RCRegClass);
 
-    DebugLoc dl = MI.getDebugLoc();
-    BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
+    DebugLoc Dl = MI.getDebugLoc();
+    BuildMI(*BB, MI, Dl, TII->get(Opcode), Dest)
         .addReg(MI.getOperand(1).getReg())
         .addImm(1);
-    BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
+    BuildMI(*BB, MI, Dl, TII->get(TargetOpcode::COPY),
             MI.getOperand(0).getReg())
-        .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
+        .addReg(IsEQ ? PPC::CR0EQ : PPC::CR0GT);
   } else if (MI.getOpcode() == PPC::TCHECK_RET) {
     DebugLoc Dl = MI.getDebugLoc();
     MachineRegisterInfo &RegInfo = F->getRegInfo();