[PATCH] D71921: [NFC] [PowerPC] Use isPredicable bits in instruction definitions

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added a comment.

In D71921#1799539 <https://reviews.llvm.org/D71921#1799539>, @jsji wrote:

> > I checked all references to `isPredicable` in codebase:
> > 
> > - Instr doc generation uses the bit (this is non-functional)
> > - CodeGen tablegen itself uses it
> > - Both `TargetInstrInfo::isUnpredicatedTerminator` and `TargetInstrInfo::PredicateInstruction` references the method, but PPC overrides them and doesn't use it.
> > - `MachineInstr::findFirstPredOperandIdx` references it, but only ARM and AMDGPU invokes it
> > - Implicit null check <https://github.com/llvm/llvm-project/blob/266cd7717c8126213a7560d26da5495053be90c0/llvm/lib/CodeGen/ImplicitNullChecks.cpp#L375> and machine sink <https://github.com/llvm/llvm-project/blob/266cd7717c8126213a7560d26da5495053be90c0/llvm/lib/CodeGen/MachineSink.cpp#L773> have referenced it. However, this patch won't touch instrs may load or store, so result of expression would never change
> > - Other references are for other platforms
>
> So, I assume you are saying this is *NFC* for PowerPC, right?


Yes. I changed title of this revision.


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