[llvm] 491cfa4 - AMDGPU/GlobalISel: Account for G_PHI result bank
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 30 07:24:59 PST 2019
Author: Matt Arsenault
Date: 2019-12-30T09:55:21-05:00
New Revision: 491cfa4250d7a146131202ad33878ba398c7ae87
URL: https://github.com/llvm/llvm-project/commit/491cfa4250d7a146131202ad33878ba398c7ae87
DIFF: https://github.com/llvm/llvm-project/commit/491cfa4250d7a146131202ad33878ba398c7ae87.diff
LOG: AMDGPU/GlobalISel: Account for G_PHI result bank
Sometimes the result bank of the phi is already assigned to something,
and should not be ignored. This is in preparation for additional
boolean phi handling changes.
Also refine the logic to fix some cases that were incorrectly deciding
to use SGPRs.
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 7463ed8fcd57..0006d16c3545 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -2100,6 +2100,21 @@ static unsigned regBankUnion(unsigned RB0, unsigned RB1) {
AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
}
+static int regBankBoolUnion(int RB0, int RB1) {
+ if (RB0 == -1)
+ return RB1;
+ if (RB1 == -1)
+ return RB0;
+
+ // vcc, vcc -> vcc
+ if (RB0 == AMDGPU::VCCRegBankID && RB1 == AMDGPU::VCCRegBankID)
+ return AMDGPU::VCCRegBankID;
+
+ // vcc, sgpr -> vgpr
+ // vcc, vgpr -> vgpr
+ return regBankUnion(RB0, RB1);
+}
+
const RegisterBankInfo::ValueMapping *
AMDGPURegisterBankInfo::getSGPROpMapping(Register Reg,
const MachineRegisterInfo &MRI,
@@ -2167,6 +2182,11 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
if (MI.getOpcode() == TargetOpcode::G_PHI) {
// TODO: Generate proper invalid bank enum.
int ResultBank = -1;
+ Register DstReg = MI.getOperand(0).getReg();
+
+ // Sometimes the result may have already been assigned a bank.
+ if (const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI))
+ ResultBank = DstBank->getID();
for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
Register Reg = MI.getOperand(I).getReg();
@@ -2179,25 +2199,15 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
}
unsigned OpBank = Bank->getID();
- // scc, scc -> sgpr
- if (OpBank == AMDGPU::SCCRegBankID) {
- // There's only one SCC register, so a phi requires copying to SGPR.
+ if (OpBank == AMDGPU::SCCRegBankID)
OpBank = AMDGPU::SGPRRegBankID;
- } else if (OpBank == AMDGPU::VCCRegBankID) {
- // vcc, vcc -> vcc
- // vcc, sgpr -> vgpr
- if (ResultBank != -1 && ResultBank != AMDGPU::VCCRegBankID) {
- ResultBank = AMDGPU::VGPRRegBankID;
- break;
- }
- }
- ResultBank = OpBank;
+ ResultBank = regBankBoolUnion(ResultBank, OpBank);
}
assert(ResultBank != -1);
- unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
+ unsigned Size = MRI.getType(DstReg).getSizeInBits();
const ValueMapping &ValMap =
getValueMapping(0, Size, getRegBank(ResultBank));
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
index d1aa28d445d0..0b01ad986487 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
@@ -287,9 +287,11 @@ body: |
; FAST: [[ICMP2:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; FAST: G_BR %bb.2
; FAST: bb.2:
- ; FAST: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
- ; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[PHI]](s1)
- ; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[COPY3]](s1), [[C]], [[COPY1]]
+ ; FAST: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
+ ; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
+ ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
; GREEDY-LABEL: name: phi_s1_vcc_scc_sbranch
; GREEDY: bb.0:
@@ -308,7 +310,7 @@ body: |
; GREEDY: [[ICMP2:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GREEDY: G_BR %bb.2
; GREEDY: bb.2:
- ; GREEDY: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
+ ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
@@ -743,7 +745,7 @@ body: |
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: G_BR %bb.2
; FAST: bb.2:
- ; FAST: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
+ ; FAST: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]
@@ -765,7 +767,7 @@ body: |
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: G_BR %bb.2
; GREEDY: bb.2:
- ; GREEDY: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
+ ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]
@@ -1331,3 +1333,85 @@ body: |
S_SETPC_B64 undef $sgpr30_sgpr31, implicit %8
...
+
+---
+name: phi_s1_vcc_result_scc_scc_sbranch
+legalized: true
+tracksRegLiveness: true
+
+body: |
+ ; FAST-LABEL: name: phi_s1_vcc_result_scc_scc_sbranch
+ ; FAST: bb.0:
+ ; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; FAST: liveins: $sgpr0, $sgpr1, $sgpr2
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
+ ; FAST: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; FAST: G_BRCOND [[ICMP1]](s1), %bb.1
+ ; FAST: G_BR %bb.2
+ ; FAST: bb.1:
+ ; FAST: successors: %bb.2(0x80000000)
+ ; FAST: [[ICMP2:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; FAST: G_BR %bb.2
+ ; FAST: bb.2:
+ ; FAST: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
+ ; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
+ ; FAST: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 123
+ ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
+ ; FAST: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 456
+ ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)
+ ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
+ ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ; GREEDY-LABEL: name: phi_s1_vcc_result_scc_scc_sbranch
+ ; GREEDY: bb.0:
+ ; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GREEDY: liveins: $sgpr0, $sgpr1, $sgpr2
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
+ ; GREEDY: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; GREEDY: G_BRCOND [[ICMP1]](s1), %bb.1
+ ; GREEDY: G_BR %bb.2
+ ; GREEDY: bb.1:
+ ; GREEDY: successors: %bb.2(0x80000000)
+ ; GREEDY: [[ICMP2:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; GREEDY: G_BR %bb.2
+ ; GREEDY: bb.2:
+ ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
+ ; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
+ ; GREEDY: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 123
+ ; GREEDY: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 456
+ ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[C1]], [[C2]]
+ ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $sgpr0, $sgpr1, $sgpr2
+
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = COPY $sgpr2
+ %3:_(s32) = G_CONSTANT i32 0
+ %4:_(s1) = G_ICMP intpred(eq), %0, %3
+ %5:_(s1) = G_ICMP intpred(eq), %2, %3
+ G_BRCOND %5, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %6:_(s1) = G_ICMP intpred(eq), %1, %3
+ G_BR %bb.2
+
+ bb.2:
+ %7:vcc(s1) = G_PHI %4, %bb.0, %6, %bb.1
+ %8:vgpr(s32) = G_CONSTANT i32 123
+ %9:vgpr(s32) = G_CONSTANT i32 456
+ %10:vgpr(s32) = G_SELECT %7, %8, %9
+ S_SETPC_B64 undef $sgpr30_sgpr31, implicit %10
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
index bd6bc57c633c..3d90e03addd1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
@@ -838,9 +838,11 @@ body: |
; FAST: [[ICMP2:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; FAST: G_BR %bb.2
; FAST: bb.2:
- ; FAST: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
- ; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[PHI]](s1)
- ; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[COPY3]](s1), [[C]], [[COPY1]]
+ ; FAST: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
+ ; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
+ ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
; GREEDY-LABEL: name: phi_s1_vcc_scc_sbranch
; GREEDY: bb.0:
@@ -859,7 +861,7 @@ body: |
; GREEDY: [[ICMP2:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GREEDY: G_BR %bb.2
; GREEDY: bb.2:
- ; GREEDY: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
+ ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
@@ -1294,7 +1296,7 @@ body: |
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: G_BR %bb.2
; FAST: bb.2:
- ; FAST: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
+ ; FAST: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]
@@ -1316,7 +1318,7 @@ body: |
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: G_BR %bb.2
; GREEDY: bb.2:
- ; GREEDY: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
+ ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]
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