[PATCH] D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:2931
+  if (auto CNode = dyn_cast<ConstantSDNode>(N)) {
+    uint64_t ImmVal = CNode->getSExtValue();
+    SDLoc DL(N);
----------------
Should this be zero extended (`getZExtValue`)?


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:215
 
+def SVEArithImmPat  : ComplexPattern<i32, 1, "SelectSVEArithImm", []>;
+def SVESArithImmPat : ComplexPattern<i32, 1, "SelectSVESignedArithImm", []>;
----------------
`SVEUArithImmPat`?


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Comment at: llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll:8
+; CHECK-LABEL: smax_i8_pos
+; CHECK: // %bb.0:
+; CHECK-NEXT: smax z0.b, z0.b, #27
----------------
the BB check can be removed


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71779/new/

https://reviews.llvm.org/D71779