[PATCH] D71921: [PowerPC] Use isPredicable bits in instruction definitions

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added a comment.

In D71921#1798444 <https://reviews.llvm.org/D71921#1798444>, @steven.zhang wrote:

> You need to revisit the place that use the isPredicable bit of the MI, which might cause functionality change.




In D71921#1797240 <https://reviews.llvm.org/D71921#1797240>, @jsji wrote:

> If this is a NFC change, please add [NFC] in summary. Or else, please add test. Thanks.


I checked all references to `isPredicable` in codebase:

- Instr doc generation uses the bit (this is non-functional)
- CodeGen tablegen itself uses it
- Both `TargetInstrInfo::isUnpredicatedTerminator` and `TargetInstrInfo::PredicateInstruction` references the method, but PPC overrides them and doesn't use it.
- `MachineInstr::findFirstPredOperandIdx` references it, but only ARM and AMDGPU invokes it
- Implicit null check <https://github.com/llvm/llvm-project/blob/266cd7717c8126213a7560d26da5495053be90c0/llvm/lib/CodeGen/ImplicitNullChecks.cpp#L375> and machine sink <https://github.com/llvm/llvm-project/blob/266cd7717c8126213a7560d26da5495053be90c0/llvm/lib/CodeGen/MachineSink.cpp#L773> have referenced it. However, this patch won't touch instrs may load or store, so result of expression would never change
- Other references are for other platforms


Repository:
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https://reviews.llvm.org/D71921