[PATCH] D71983: [PowerPC] Set the SideEffects of branch & call instructions from 1 to 0

[Zhang Kang via Phabricator via llvm-commits]

ZhangKang created this revision.
ZhangKang added reviewers: hfinkel, PowerPC.
Herald added subscribers: shchenz, wuzish, nemanjai.
Herald added a project: LLVM.

If we didn't set the value for hasSideEffects bit in our td file,  `llvm-tblgen` will set it as true for those instructions which has no match pattern. 
But for branch & call instructions, PPC can model, so those instructions don't need the hasSideEffects flag.

This patch is to set the SideEffects of branch & call instructions from 1 to 0. The SideEffects flag of below instructions have been set from 1 to 0:

Below instructions can be generated:

  BCC
  BCCCTR
  BCCCTR8
  BCCCTRL
  BCCCTRL8
  BCCLR
  BCCTR
  BCCTR8
  BCCTR8n
  BCCTRL
  BCCTRL8
  BCCTRL8n
  BCCTRLn
  BCCTRn
  BCLR
  BCLRn
  BCLalways
  BCTR
  BCTR8
  BDNZ
  BDNZ8
  BDNZLR
  BDNZLR8
  BDZ
  BDZ8
  BDZLR
  BDZLR8
  BL8_NOP_TLS
  BL_TLS
  CTRL_DEP
  TAILB
  TAILB8
  TAILBA
  TAILBA8
  TAILBCTR
  TAILBCTR8

Below instructions can't be generated:

  BA
  BCL
  BCLRL
  BCLRLn
  BCLn
  BDNZA
  BDNZAm
  BDNZAp
  BDNZL
  BDNZLA
  BDNZLAm
  BDNZLAp
  BDNZLRL
  BDNZLRLm
  BDNZLRLp
  BDNZLRm
  BDNZLRp
  BDNZLm
  BDNZLp
  BDNZm
  BDNZp
  BDZA
  BDZAm
  BDZAp
  BDZL
  BDZLA
  BDZLAm
  BDZLAp
  BDZLRL
  BDZLRLm
  BDZLRLp
  BDZLRm
  BDZLRp
  BDZLm
  BDZLp
  BDZm
  BDZwap
  BL8_TLS
  BL8_TLS_
  BLRL
  
  BCCA
  BCCL
  BCCLA
  BCCLRL
  gBC
  gBCA
  gBCAat
  gBCCTR
  gBCCTRL
  gBCL
  gBCLA
  gBCLAat
  gBCLR
  gBCLRL
  gBCLat
  gBCat


https://reviews.llvm.org/D71983

Files:
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td

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