[PATCH] D71934: [AMDGPU] need to insert wait between the scalar load and vector store to the same address to avoid WAR conflict.

[Alexander via Phabricator via llvm-commits]

alex-t created this revision.
alex-t added reviewers: rampitec, vpykhtin, nhaehnle.
Herald added subscribers: hiraditya, t-tye, tpr, dstuttard, yaxunl, wdng, jvesely, kzhuravl, arsenm.
Herald added a project: LLVM.
alex-t edited the summary of this revision.

Before divergence driven ISel introduced scalar loads from the global address space we relied on the VMEM operations ordering enforced by the HW. Now we can easily get WAR on scalar load followed vector store to same address.
The case is here:   https://github.com/RadeonOpenCompute/ROCm/issues/500

Current fix relies on the MachineMemOperands equality to check that SMRD and VMEM use same address.
Proper fix should include creating the alias analysis on the machine IR that is obviously too big hummer at the moment.


https://reviews.llvm.org/D71934

Files:
  llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  llvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll

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