[PATCH] D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant.

[qshanz via Phabricator via llvm-commits]

steven.zhang marked an inline comment as done.
steven.zhang added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll:10
   %4 = ashr exact i64 %3, 48
-; CHECK: ANDI8o killed {{[^,]+}}, 65520, implicit-def dead $cr0
+; CHECK: RLWINM8 killed %3:g8rc, 0, 16, 27
 ; CHECK: CMPLDI
----------------
shchenz wrote:
> The case change seems strange here, the left uses a record form ANDI8, so we can eliminate the CMPLDI with 0 after peephole. But with this change,  ANDI8 is converted to RLWINM8, which is not record form. but it surprises me we still can delete the CMPLDI with 0 and replace RLWINM8 back with ANDI8. I think here we should use record form RLWINM8o. But I think it is not this patch's scope.
If it is NOT 16 bit, it is transformed to RLWINM8 record form. And it makes sense to me.
```
define signext i32 @fn1(i32 %baz) {
  %1 = mul nsw i32 %baz, 208
  %2 = zext i32 %1 to i64
  %3 = shl i64 %2, 47
  %4 = ashr exact i64 %3, 47
  %5 = icmp eq i64 %4, 0
  br i1 %5, label %foo, label %bar
foo:
  ret i32 1

bar:
  ret i32 0
}
```

```
	mulli 3, 3, 208
	rlwinm. 3, 3, 0, 15, 27
	beq	0, .LBB0_2
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71829/new/

https://reviews.llvm.org/D71829