[PATCH] D71879: [X86] Custom widen 128/256-bit vXi32 fp_to_uint on avx512f targets without avx512vl. Similar for vXi64 on avx512dq without avx512vl.

[Pengfei Wang via Phabricator via llvm-commits]

pengfei added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:19811-19812
+    if (VT == MVT::v8i32 && SrcVT == MVT::v8f64) {
+      assert(!IsSigned && "Expected unsigned conversion!");
+      assert(Subtarget.useAVX512Regs() && "Requires avx512f");
+      return Op;
----------------
Why no signed, they are legal too.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:19837-19839
+      } else {
+        Res = DAG.getNode(ISD::FP_TO_UINT, dl, ResVT, Src);
+      }
----------------
Remove curly braces.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:19868-19870
+      } else {
+        Res = DAG.getNode(Op.getOpcode(), dl, MVT::v8i64, Src);
+      }
----------------
Remove curly braces.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:19883
       SDValue Tmp = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32, Src,
                                 DAG.getUNDEF(MVT::v2f32));
       if (IsStrict) {
----------------
Need pad zero for strict.


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Comment at: llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll:1122
 ; AVX512DQ:       # %bb.0:
 ; AVX512DQ-NEXT:    vcvttps2dq %ymm0, %ymm0
 ; AVX512DQ-NEXT:    vpmovdw %zmm0, %ymm0
----------------
There're tests for AVX512DQ that don't use zmm registers, I guess the actions for them are not correctly set.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D71879/new/

https://reviews.llvm.org/D71879