[PATCH] D71778: [RISCV] Add Clang Builtins for Accessing CSRs

[Sam Elliott via Phabricator via llvm-commits]

lenary created this revision.
lenary added reviewers: asb, luismarques.
Herald added subscribers: llvm-commits, cfe-commits, apazos, sameer.abuasal, pzheng, s.egerton, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
Herald added projects: clang, LLVM.

As of clang 9.0, the only way to access the RISC-V Control and Status Registers
is to use inline assembly, which is ugly and hinders optimisations.

This patch adds some Clang Builtins and LLVM Intrinsics to allow programmers
to access the CSRs without using inline assembly, which should therefore be
safer.

I hope to build a slightly nicer interface to this, to support the read-only or
write-only CSR operations (akin to the `csrr`, `csrw`, `csrs` and `csrc`
pseudo-instructions) via these builtins, which will eventually be available via
`<rvintrin.h>`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D71778

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/TargetBuiltins.h
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/riscv-csr-builtins.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp
  llvm/test/CodeGen/RISCV/intrinsics/csr_accesses_rv32.ll
  llvm/test/CodeGen/RISCV/intrinsics/csr_accesses_rv64.ll

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