[PATCH] D71774: [RISCV] Optimize seteq/setne pattern expansions for better code size

[weiwei via Phabricator via llvm-commits]

wwei created this revision.
wwei added reviewers: asb, lenary, lewis-revill, simoncook, rogfer01.
wwei added a project: LLVM.
Herald added subscribers: llvm-commits, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, johnrusso, rbar, hiraditya.

ADDI(C.ADDI) may achieve better code size than XORI, since XORI has no C extension.
This patch transforms two patterns and gets almost equivalent results.


Repository:
  rL LLVM

https://reviews.llvm.org/D71774

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/i32-icmp.ll
  llvm/test/CodeGen/RISCV/setcc-logic.ll

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