[llvm] 9d1071e - [NFC][Test][PowerPC] Add more tests for 'and mask'

[QingShan Zhang via llvm-commits]

Author: QingShan Zhang
Date: 2019-12-23T06:59:14Z
New Revision: 9d1071eac401830b07edf3e3ca91c40f1df112d7

URL: https://github.com/llvm/llvm-project/commit/9d1071eac401830b07edf3e3ca91c40f1df112d7
DIFF: https://github.com/llvm/llvm-project/commit/9d1071eac401830b07edf3e3ca91c40f1df112d7.diff

LOG: [NFC][Test][PowerPC] Add more tests for 'and mask'

Added: 
    llvm/test/CodeGen/PowerPC/and-mask.ll

Modified: 
    llvm/test/CodeGen/PowerPC/shift_mask.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/PowerPC/and-mask.ll b/llvm/test/CodeGen/PowerPC/and-mask.ll
new file mode 100644
index 000000000000..886657185301
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/and-mask.ll
@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+; mask 0xFFFFFFFE
+define i32 @test1(i32 %a) {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lis 4, 32767
+; CHECK-NEXT:    ori 4, 4, 65535
+; CHECK-NEXT:    sldi 4, 4, 1
+; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    blr
+  %and = and i32 %a, -2
+  ret i32 %and
+}
+
+; mask 0xFFFFFFFFFFFFFFF9
+define i64 @test2(i64 %a) {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, -7
+; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    blr
+  %and = and i64 %a, -7
+  ret i64 %and
+}
+
+; mask: 0xFFFFFFC00000
+define i64 @test3(i64 %a) {
+; CHECK-LABEL: test3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lis 4, 1023
+; CHECK-NEXT:    ori 4, 4, 65535
+; CHECK-NEXT:    sldi 4, 4, 22
+; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    blr
+  %and = and i64 %a, 281474972516352
+  ret i64 %and
+}
+
+; mask: 0xC000000FF
+define i64 @test4(i64 %a) {
+; CHECK-LABEL: test4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, 12
+; CHECK-NEXT:    sldi 4, 4, 32
+; CHECK-NEXT:    ori 4, 4, 255
+; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    blr
+  %and = and i64 %a, 51539607807
+  ret i64 %and
+}
+
+; mask: 0xFFC0FFFF
+define i64 @test5(i64 %a) {
+; CHECK-LABEL: test5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, 0
+; CHECK-NEXT:    oris 4, 4, 65472
+; CHECK-NEXT:    ori 4, 4, 65535
+; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    blr
+  %and = and i64 %a, 4290838527
+  ret i64 %and
+}
+
+; mask: 0x3FC0FFE0
+define i64 @test6(i64 %a) {
+; CHECK-LABEL: test6:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lis 4, 16320
+; CHECK-NEXT:    ori 4, 4, 65504
+; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    blr
+  %and = and i64 %a, 1069613024
+  ret i64 %and
+}
+
+; mask: 0x3FC000001FFFF
+define i64 @test7(i64 %a) {
+; CHECK-LABEL: test7:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, -32767
+; CHECK-NEXT:    sldi 4, 4, 32
+; CHECK-NEXT:    oris 4, 4, 65024
+; CHECK-NEXT:    rldicr 4, 4, 17, 63
+; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    blr
+  %and = and i64 %a, 1121501860462591
+  ret i64 %and
+}

diff  --git a/llvm/test/CodeGen/PowerPC/shift_mask.ll b/llvm/test/CodeGen/PowerPC/shift_mask.ll
index ebd30926ca76..59382c615311 100644
--- a/llvm/test/CodeGen/PowerPC/shift_mask.ll
+++ b/llvm/test/CodeGen/PowerPC/shift_mask.ll
@@ -257,25 +257,3 @@ define <2 x i64> @test213(<2 x i64> %a, <2 x i64> %b) {
   %ashr = ashr <2 x i64> %a, %rem
   ret <2 x i64> %ashr
 }
-
-define i32 @test214(i32 %a) {
-; CHECK-LABEL: test214:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    lis 4, 32767
-; CHECK-NEXT:    ori 4, 4, 65535
-; CHECK-NEXT:    sldi 4, 4, 1
-; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    blr
-  %and = and i32 %a, -2
-  ret i32 %and
-}
-
-define i64 @test215(i64 %a) {
-; CHECK-LABEL: test215:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 4, -7
-; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    blr
-  %and = and i64 %a, -7
-  ret i64 %and
-}