[PATCH] D71715: [AArch64][SVE] Correct intrinsics and patterns for logical predicate instructions

[Paul Walker via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6cba90dc4de6: [AArch64][SVE] Correct intrinsics and patterns for logical predicate… (authored by paulwalker-arm).

Changed prior to commit:
  https://reviews.llvm.org/D71715?vs=234742&id=234888#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71715/new/

https://reviews.llvm.org/D71715

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-int-log-pred.ll
  llvm/test/CodeGen/AArch64/sve-int-log.ll
  llvm/test/CodeGen/AArch64/sve-pred-log.ll

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