[PATCH] D71749: [ARM] Specify address mode of pseudo instruction LOADDUAL

[Victor Campos via Phabricator via llvm-commits]

vhscampos created this revision.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls.
Herald added a project: LLVM.
vhscampos added a reviewer: efriedma.

LOADDUAL did not have an address mode specified. As such, places that
were expecting one were failing, e.g. in ARMFrameLowering when LOADDUAL
was used to reference a stack frame.

This patch adds an Address Mode to the LOADDUAL pseudoinstruction in its
TableGen definition.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D71749

Files:
  llvm/lib/Target/ARM/ARMInstrInfo.td


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrInfo.td
+++ llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -2704,7 +2704,9 @@
 let mayLoad = 1, hasSideEffects = 0, hasNoSchedulingInfo = 1 in {
 def LOADDUAL : ARMPseudoInst<(outs GPRPairOp:$Rt), (ins addrmode3:$addr),
                              64, IIC_iLoad_d_r, []>,
-               Requires<[IsARM, HasV5TE]>;
+               Requires<[IsARM, HasV5TE]> {
+  let AM = AddrMode3;
+}
 }
 
 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),


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