[PATCH] D71715: [AArch64][SVE] Correct intrinsics and patterns for logical predicate instructions

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm created this revision.
paulwalker-arm added reviewers: eli.friedman, sdesmalen, dancgr.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.

  In general SVE intrinsics are considered predicated and merging
  with everything else having suitable decoration.  For predicated
  zeroing operations (like the predicate logical instructions) we
  use the "_z" suffix.  After this change all intrinsics use their
  expected names (i.e. orr instead of or and eor instead of xor).
  
  I've removed intrinsics and patterns for condition code setting
  instructions as that data is not returned as part of the intrinsic.
  The expectation is to ask for a cc flag explicitly.
  
  For example:
    a = and_z(pg, p1, p2)
    cc = ptest_<flag>(pg, a)
  
  With the code generator expected to use "s" variants of instructions
  when available.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D71715

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-int-log-pred.ll
  llvm/test/CodeGen/AArch64/sve-int-log.ll
  llvm/test/CodeGen/AArch64/sve-pred-log.ll

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