[PATCH] D71492: [SCEV] Generate AddRec for trivial and LCSSA phis outside of loop header.

[Bardia Mahjour via Phabricator via llvm-commits]

bmahjour updated this revision to Diff 234615.
bmahjour marked 5 inline comments as done.
bmahjour added a comment.

Address Michael's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71492/new/

https://reviews.llvm.org/D71492

Files:
  llvm/lib/Analysis/ScalarEvolution.cpp
  llvm/test/Analysis/ScalarEvolution/solve-quadratic-i1.ll
  llvm/test/Analysis/ScalarEvolution/solve-quadratic-overflow.ll
  llvm/test/Analysis/ScalarEvolution/trivial-phis.ll
  llvm/test/Transforms/IndVarSimplify/lftr-pr20680.ll
  llvm/test/Transforms/LoopIdiom/scev-invalidation.ll
  llvm/test/Transforms/LoopStrengthReduce/funclet.ll

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