[PATCH] D71672: [AArch64] match splat of bitcasted extract subvector to DUPLANE

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7045
     // to make a vector of the same size as this SHUFFLE. We can ignore the
     // extract entirely, and canonicalise the concat using WidenVector.
+    unsigned VTEltBitWidth = VT.getScalarSizeInBits();
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Can you fix the comments here, so each of these transforms has its own comment briefly explaining what it does?

`V1.getOperand(0).getScalarValueSizeInBits() % VTEltBitWidth == 0` seems overly restrictive.  I guess you have to enforce that the EXTRACT_SUBVECTOR index is appropriately aligned, but it would be okay to allow, for example, `<16 x i8>` with index 8.  Maybe translate the EXTRACT_SUBVECTOR index to a byte offset, then divide by the element size of the result?  That should also make the logic a little easier to follow.


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  https://reviews.llvm.org/D71672/new/

https://reviews.llvm.org/D71672