[PATCH] D71589: [PowerPC] Adding a match pattern to recognize the and mask with RLWINM8

[qshanz via Phabricator via llvm-commits]

steven.zhang updated this revision to Diff 234481.
steven.zhang added a comment.

Update the patch as one critical bug was found.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71589/new/

https://reviews.llvm.org/D71589

Files:
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/cmpb.ll
  llvm/test/CodeGen/PowerPC/shift_mask.ll


Index: llvm/test/CodeGen/PowerPC/shift_mask.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/shift_mask.ll
+++ llvm/test/CodeGen/PowerPC/shift_mask.ll
@@ -261,10 +261,7 @@
 define i32 @test214(i32 %a) {
 ; CHECK-LABEL: test214:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lis 4, 32767
-; CHECK-NEXT:    ori 4, 4, 65535
-; CHECK-NEXT:    sldi 4, 4, 1
-; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    rlwinm 3, 3, 0, 0, 30
 ; CHECK-NEXT:    blr
   %and = and i32 %a, -2
   ret i32 %and
Index: llvm/test/CodeGen/PowerPC/cmpb.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/cmpb.ll
+++ llvm/test/CodeGen/PowerPC/cmpb.ll
@@ -123,11 +123,8 @@
   ret i32 %or55
 
 ; CHECK-LABEL: @test32p1
-; CHECK: li [[REG1:[0-9]+]], 0
 ; CHECK: cmpb [[REG4:[0-9]+]], 4, 3
-; CHECK: oris [[REG2:[0-9]+]], [[REG1]], 65287
-; CHECK: ori [[REG3:[0-9]+]], [[REG2]], 65535
-; CHECK: and 3, [[REG4]], [[REG3]]
+; CHECK: rlwinm 3, [[REG4]], 0, 13, 7 
 ; CHECK: blr
 }
 
@@ -147,11 +144,8 @@
   ret i32 %or37
 
 ; CHECK-LABEL: @test32p2
-; CHECK: li [[REG1:[0-9]+]], 0
 ; CHECK: cmpb [[REG4:[0-9]+]], 4, 3
-; CHECK: oris [[REG2:[0-9]+]], [[REG1]], 65280
-; CHECK: ori [[REG3:[0-9]+]], [[REG2]], 65535
-; CHECK: and 3, [[REG4]], [[REG3]]
+; CHECK: rlwinm 3, [[REG4]], 0, 16, 7 
 ; CHECK: blr
 }
 
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -376,6 +376,18 @@
     return false;
 }]>;
 
+def maskimm64 : PatLeaf<(imm), [{
+  // maskImm predicate - True if immediate is a run of ones.
+  unsigned mb, me;
+  if (N->getValueType(0) == MVT::i64) {
+    // High 32-bit need to be zero.
+    uint64_t Mask = (uint64_t)N->getZExtValue();
+    return isUInt<32>(Mask) && isRunOfOnes((unsigned)Mask, mb, me);
+  }
+  else
+    return false;
+}]>;
+
 def imm32SExt16  : Operand<i32>, ImmLeaf<i32, [{
   // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
   // sign extended field.  Used by instructions like 'addi'.
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1355,6 +1355,10 @@
 def : Pat<(i32 (trunc i64:$in)),
           (EXTRACT_SUBREG $in, sub_32)>;
 
+// RLWINM8
+def : Pat<(and i64:$in, maskimm64:$imm),
+          (RLWINM8 $in, 0, (MB maskimm64:$imm), (ME maskimm64:$imm))>;
+
 // Implement the 'not' operation with the NOR instruction.
 // (we could use the default xori pattern, but nor has lower latency on some
 // cores (such as the A2)).


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