[PATCH] D71515: [AArch64] match fcvtl2 with bitcasted extract

[Sanjay Patel via Phabricator via llvm-commits]

spatel marked an inline comment as done.
spatel added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:3642
+               (extract_subvector (v2i64 V128:$Rn), (i64 1))))))),
+          (FCVTLv4i32 V128:$Rn)>;
 
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efriedma wrote:
> This looks correct.
> 
> Can we generalize this to handle the top half of any 128-bit vector, somehow?  Extending the set of special cases to include v2i64 in addition to v4f32 doesn't seem like a complete plan.
I don't know how to hack this in tablegen, but it seems straightforward in DAGToDAGISel.


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https://reviews.llvm.org/D71515