[PATCH] D71609: [ARM][MVE] Fixes for tail predication.

[Sam Parker via Phabricator via llvm-commits]

samparker created this revision.
samparker added reviewers: dmgreen, SjoerdMeijer.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: LLVM.

1. Fix an issue with the incorrect value being used for the number of elements being passed to [d|w]lstp. We were trying to check that the value was available at LoopStart, but this doesn't consider that the last instruction in the block could also define the register! Two helpers have been added to RDA for this.
2. Insert some code to now try to move the element count def or the insertion point so that we can perform more tail predication.
3. Related to (1), the same off-by-one could prevent us from generating a low-overhead loop when a mov lr could have been the last instruction in the block.
4. Fix up some instruction attributes so that not all the low-overhead loop instructions are labelled as branches and terminators - as this is not true for dls/dlstp.


https://reviews.llvm.org/D71609

Files:
  llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
  llvm/lib/CodeGen/ReachingDefAnalysis.cpp
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D71609.234297.patch
Type: text/x-patch
Size: 37564 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20191217/4df0ad42/attachment.bin>