[PATCH] D71568: [InstCombine] `select + mul` -> `select + shl` with power of twos.
Danila Kutenin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 17 01:54:51 PST 2019
danlark updated this revision to Diff 234245.
danlark marked an inline comment as done.
danlark added a comment.
undef should return zero in select+shl
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D71568/new/
https://reviews.llvm.org/D71568
Files:
llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
llvm/test/Transforms/InstCombine/getelementptr.ll
llvm/test/Transforms/InstCombine/mul.ll
llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll
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