[PATCH] D70800: Fix AArch64 AAPCS frame record chain

[Logan Chien via Phabricator via llvm-commits]

logan reopened this revision.
logan added a comment.
This revision is now accepted and ready to land.

I reverted the CL because I encountered the following assertion:

  assert((DestReg != AArch64::SP || Bytes % 16 == 0) &&
         "SP increment/decrement not 16-byte aligned");

I will upload a revision soon.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70800/new/

https://reviews.llvm.org/D70800