[PATCH] D71568: [InstCombine] `select + mul` -> `select + shl` with power of twos.

[Danila Kutenin via Phabricator via llvm-commits]

danlark updated this revision to Diff 234183.
danlark added a comment.

Add simple min integer test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71568/new/

https://reviews.llvm.org/D71568

Files:
  llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
  llvm/test/Transforms/InstCombine/mul.ll

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