[llvm] 002adab - [AArch64][SVE] Change pattern generation code to fix -Wimplicit-fallthrough after D71483

[Fangrui Song via llvm-commits]

Author: Fangrui Song
Date: 2019-12-16T15:09:05-08:00
New Revision: 002adabb3a251a81ef304353eefb1bf96ec388f6

URL: https://github.com/llvm/llvm-project/commit/002adabb3a251a81ef304353eefb1bf96ec388f6
DIFF: https://github.com/llvm/llvm-project/commit/002adabb3a251a81ef304353eefb1bf96ec388f6.diff

LOG: [AArch64][SVE] Change pattern generation code to fix -Wimplicit-fallthrough after D71483

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index e138c2dc8601..f40652f4fbbc 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -2867,16 +2867,23 @@ bool AArch64DAGToDAGISel::SelectSVELogicalImm(SDValue N, MVT VT, SDValue &Imm) {
     switch (VT.SimpleTy) {
       case MVT::i8:
         ImmVal &= 0xFF;
-        ImmVal |= (ImmVal << 8);
+        ImmVal |= ImmVal << 8;
+        ImmVal |= ImmVal << 16;
+        ImmVal |= ImmVal << 32;
+        break;
       case MVT::i16:
         ImmVal &= 0xFFFF;
-        ImmVal |= (ImmVal << 16);
+        ImmVal |= ImmVal << 16;
+        ImmVal |= ImmVal << 32;
+        break;
       case MVT::i32:
         ImmVal &= 0xFFFFFFFF;
-        ImmVal |= (ImmVal << 32);
+        ImmVal |= ImmVal << 32;
         break;
-      default:
+      case MVT::i64:
         break;
+      default:
+        llvm_unreachable("Unexpected type");
     }
 
     uint64_t encoding;