[PATCH] D71561: [InstCombine] `select + mul` -> `select + shl` with power of 2s.

[Danila Kutenin via Phabricator via llvm-commits]

danlark created this revision.
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Now select + mul transforms to select + shl with power of 2s known in select. It was implemented in udiv but was missed for multiplication for some reason, unifying and applying.

Patch by Danila Kutenin. email:danilak at google.com, github:danlark1@


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D71561

Files:
  llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
  llvm/test/Transforms/InstCombine/mul.ll

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