[PATCH] D71390: [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0

[Jim Lin via Phabricator via llvm-commits]

Jim added a comment.

If an instruction has side effects, it would be a scheduling barrier.
Not any instruction can be scheduled crossing it.



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Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:412
                        [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
-
 let Defs = [LR8] in {
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Blank line shouldn't deleted here.


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https://reviews.llvm.org/D71390